( Post 97 Item 1 ) --------------------------------------------------
Subject: Post 96 Item 2 "Simulation/Synthesis Differing & Cryptic Warning"
>Can anyone decipher this message for me. My simulation is just fine.
>Synthesized netlist creates an X in one of the bits of my counter
>and propogates all throughtout. This is the message I get during
>my synthesis run.
>
>Warning: Variable 'late_cycle' is driven in more than one process
> or block in file counter.v. This may cause mismatch
> between simulation and synthesis. (HDL -220)
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From: parkin@ultrasparc.Eng.Sun.COM (Michael Parkin)
If a variable is assigned or driven in more than one block,
the design compiler (v2.2) will generate a wired "and" connection
using an actual AND gate in my test case. The simulation may
work fine if the assignments are mutually exclusive. If they are
not, one of the assignments will overwrite the other one. With
the generated netlist, the "AND" function will behave completely
different.
In the case of two assignments to the same variable in different
blocks, synopsys infers two separate flop-flps which are anded
together to produce a single output, which is not desired.
Solution is two put both assignments in the same block.
module test_ma(clk, load1, a1, load2, a2, q);
input clk, load1, load2, a1, a2;
output q;
reg q;
always @(posedge clk) begin
if (load1)
q <= a1;
end
always @(posedge clk) begin
if (load2)
q <= a2;
end
endmodule
Michael Parkin,
Sun Micro
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From: chmi@vertex.com (Michael Chen)
In looks like in your HDL code the 'late_cycle' signal is driven
in different processes. After the synthesis you may get a 'short' on
this signal, i.e. two gates driving same signal. That's why the gate
level simulation gives 'X'. You have to assign a signal only once in
the design to prevent mismatch between simulation and synthesis.
Michael Chen - Vertex Semiconductor: chmi@tsbvrtx.portal.com
( Post 97 Item 2 ) --------------------------------------------------
From: moss@mdd.comm.mot.com (Barry Moss)
Subject: HPGL Output of Synopsis Schematics
Has anyone found a tool which allows Synopsys schematics to be output to
an HPGL compatible plotter? I find that printing schematics to an A-size
laser printer just doesn't provide enough detail for many of my designs.
Barry Moss
Motorola - Mobile Data Division
Richmond, BC, CANADA
( Post 97 Item 3 ) --------------------------------------------------
From: epakch@epa.ericsson.se (Kenny Chow - T/HGH)
Can somebody explain briefly what is the difference between:
1. 'minimization' option in the 'set_flatten' command.
2. 'boolean optimization' option in the 'set_structure' command.
3. if 'compile' is done with neither 'set_flatten' nor 'set_structure',
Synopsys' default is to do none of 1 & 2 above. What does Synopsys
really do in terms of synthesising a circuit implementation from
the HDL code?
We found that when synthesizing a CASE statement in Verilog, with setup 3
above,
case (muxsel) //synopsys full_case parallel_case
00001 : databus = out0;
00010 : databus = out1;
00100 : databus = out2;
01000 : databus = out3;
10000 : databus = out4;
endcase
Synopsys makes an encoder which encodes 'muxsel' value to some 3-bit
equivalent address and then a decoder to 're-decode' it into 5 separate
select lines before going into AND-OR mux structure. This becomes redundant
logic and upsets the timing we want. Of course it eats up your silicon too.
So it seems that without the options, Synopsys just translate the HDL
directly to logic. At one stage, we were not aware of the effects of these
2 options and said Synopsys is rubbish.
We made a 'work around' which uses :
casex (muxsel) //synopsys full_case parallel_case
xxxx1 : databus = out0;
xxx1x : databus = out1;
xx1xx : databus = out2;
x1xxx : databus = out3;
1xxxx : databus = out4;
endcase
and we get what we want even if option 1 & 2 above are not used.
So beware folks. Anyway, I would welcome some theoretical explanations.
Kenny Chow
Ericsson Australia Pty. Ltd.
T/HGH APZ Hardware Design
( Post 97 Item 4 ) --------------------------------------------------
From: Bernd Moessner K8/DIC Tel. 1608 <bmoessne@dic.k8.rt.bosch.de>
Subject: Data from Synopsys to GDT
Is there anyone who has experience transfering Data (Schematic or
Routerfile) from Synopsys to GDT-AutoCells(Mentor) not using Autologic.
Which tools or workarounds can help me?
Bernd Moessner
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