( Post 96 Item 1 ) ------------------------------------------------------
Subject: ESNUG Post 95 Item 2 "Problems With Timing Arcs & Timing Reports"
> I have a hierarchical design in which I'd like to disable a timing
> arc contained in one of the lower-level modules and generate a new
> top-level timing report.
>
> I tried to do this, but when I generate the new timing report, the
> timing arc I disabled still shows up. What's the right way to do
> this?
>
> Also, while I'm on the subject of timing arcs, is there an easy
> way to disable timing arcs based on the name of a bussed module port
> rather than manually find all the cells that the individual bits of
> the port connect to?
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From: sgolson@trilobyte.com (Steve Golson)
Concerning your first question: this can happen if you are down in the
hierarchy when you disable the timing arc, but are at the top when you
run the timing report. You need to have current_design the same for
the disable_timing *and* the timing report.
report_design will show you all the disabled timing arcs. Run it
just before you run report_timing, and see what it says.
Concerning your last question: maybe try disable_timing on the net,
rather than the pin?
What would be nice is to find out all the pin names on a given net.
Then you can disable_timing, etc. Unfortunately I think this is
impossible. I'd *love* to be proven wrong...
Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@trilobyte.com
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From: David Tornheim
I had a similar problem with timing loops and am equally curious about
what the proper solution is. Specifically, I tried the disable_timing
command, but got the following mysterious error:
Error: Can not disable timing arcs on pins on cell MYCELLNAME. (OPT-409)
Because of the methodology our group uses, all of the timing arcs which must
be disabled come from latch blocks (which we separate from logic blocks).
As a work-around to the above problem, I used the group command so that
all latch blocks were put in one group and all logic blocks in another.
By restarting Synopsys, and loading in just the logic block group, and
setting all arrival times, I could get the timing without concerns about
timing loops through latches. This would allow a critical path
crossing several logic blocks (from different modules) to be measured and
optimized.
-David Tornheim
( Post 96 Item 2 ) ------------------------------------------------------
From: vaseem@berlioz.nsc.com (Vaseem Anjum)
Subject: Simulation and Synthesis Differing plus Vague Cryptic Warning
Hi!
Can anyone decipher this message for me. My simulation is just fine.
Synthesized netlist creates an X in one of the bits of my counter
and propogates all throughtout. This is the message I get during
my synthesis run.
Warning: Variable 'late_cycle' is driven in more than one process
or block in file counter.v. This may cause mismatch
between simulation and synthesis. (HDL -220)
Any pointers appreciated.
Regards,
Vaseem...
( Post 96 Item 3 ) ------------------------------------------------------
Subject: Post 95 Item 1 "How To Use A User-Defined Library"
>How to use a user-defined library like "use WORK.components.all"?
>
>How to set the "WORK" directory? Do I place all the library files
>in the "WORK" directory? (All the library files are *.sim or *.mra,
>which are used in doing the gate-level simulation)
>
>In a word, how can I use the gate-level simulation library by using
>the code like that "use WORK.components.all" ?
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From: perrys@ichips.intel.com (Perry Stultz)
Q-- How to set the "WORK" directory?
A-- To set the work directory for any standard directory
on your system, add the following two lines to your
vhdl.uof file which should be in your current working
directory.
work > default
default : ./working
The entry ./working can be any valid unix path/directory.
By having this in your vhdl.uof file, the program vhdlan
will place all your *.mra and *.sim files in the
./working directory. Your simulator will then look
in the directory for all needed file.
The only time you should need to reference this directory
work is in a configuration directory.
Hope this helps.
Perry S. Stultz
Intel Corporation, Microprocessor Division 6
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