( Post 95 Item 1 ) ------------------------------------------------------

From: cmh82@cad8.cme.ncku.edu.tw ( M.H Chang )
Subject: How To Use A User-Defined Library

Hi! I am a Synopsys user.  I am eager to use the Synopsys tools, so 
I am very glad to join the group.  By discussing with E-mail, I hope 
everybody gets something from the group.

I am describing a chip by using VHDL, and I want to synthesize 
it out by using Synopsys Compiler.  I have problems with the 
following:

How to use a user-defined library like "use WORK.components.all"?

How to set the "WORK" directory?  Do I place all the library files
in the "WORK" directory? (All the library files are *.sim or *.mra,
which are used in doing the gate-level simulation)

In a word, how can I use the gate-level simulation library by using
the code like that "use WORK.components.all" ?

If somebody else can answer these problems for me, I will be very 
grateful.

Thanks in advance!!

     --  M.H Chang, ROC,Taiwan,Tainan.


( Post 95 Item 2 ) ------------------------------------------------------

From: Jerrold Pianin <pianin@BBN.COM>
Subject: Problems With Timing Arcs & Timinig Reports

I have a hierarchical design in which I'd like to disable a timing
arc contained in one of the lower-level modules and generate a new
top-level timing report.  

I tried to do this, but when I generate the new timing report, the
timing arc I disabled still shows up.  What's the right way to do
this?

Also, while I'm on the subject of timing arcs, is there an easy 
way to disable timing arcs based on the name of a bussed module port
rather than manually find all the cells that the individual bits of
the port connect to?


( Post 95 Item 3 ) ------------------------------------------------------

From: sgolson@trilobyte.com (Steve Golson)
Warning: Not All Fanouts Are The Same!

I came across this problem while trying to generate a new wireload model.
This required creating (fanout,capacitance) values for every net in a
placed&routed&extracted netlist, and then doing a statistical analysis 
on them.

So, how do you get the "fanout" values for a net? The Synopsys report_net
command gives you results like:

Net                 Fanout     Fanin      Load   Resistance    Pins   Attributes
--------------------------------------------------------------------------------
n91                      8         1      0.38         0.00       9   
n94                      1         1      0.05         0.00       2   
n97                      1         1      0.05         0.00       2   
n98                      5         1      0.29         0.00       6   

which looks like what we need. Just use the "Fanout" numbers, right?

Nope. In this case "Fanout" means "the number of pins capable of driving
the net" (i.e. the number of outputs on the net). What the wireload models
mean by "fanout" is "one less than the total number of pins on the net".
So to use report_net to find "wireload fanouts" what we really should use
is "Pins - 1".

Then there is "fanout_load" and "max_fanout" which use yet a third
definition.

   Moral: Be aware of the context in which you use "fanouts".
          This isn't a bug, just a collision of definitions.

Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@trilobyte.com



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