( Post 94 Item 1 ) ------------------------------------------------------
Subject: ESNUG Post 93 Item 2 "Mixing Cadence & Synopsys along with routing"
> Has anyone experienced trouble using Cadence's Gate Ensemble with
> Synopsys? We are having trouble with the placement in that it
> bunches cells together rather than spread them through the routing
> region. The layout engineer has had this trouble on another
> synthesized design, and reports that it was solved by re-synthesizing
> with another synthesis tool. Our design is large, and has lots of
> speed critical areas.
>
> Synopsys, Inc. has suggested that routing difficulty is typical of
> these sorts of designs. Does anyone have any ideas ...
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From: vishin@Eng.Sun.COM (Sanjay Vishin)
I came across a similar problem while working on a timing critical
design. The problem was that placement & synthesis seem to work
against each other sometimes.
In our case the problem was with Synopsys as a synthesis tool and
GDT(Mentor) as a standard cell placement tool(And Cadence's block
placement tool).
An example would be that the min-cut placer would somtimes put
nodes with low fanouts far apart(which is fine to reduce area).
The problem was that if these cells were complex cells with
weak drivers, the net delay (to drive the long wire), became
quite excessive and used to show up in critical paths.
The optimal solution would be a layout based synthesis tool.
But for the present we wrote some scripts to insert buffers
to patch up these nets. Ideally you can back annotate into synopsys
and let synopsys buffer these nodes, but there is no guarantee that
the placer will maintain the same structure when you re-route.
For the next project I worked on I decided to break blocks into
smaller standardcell blocks, and so far I haven't come across any
such problems.
The drive strength of the complex (AOI/OAI) cells is also better.
Sanjay Vishin
Sun Micro
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From: [ A User Who Wishes To Remain Anonymous ]
One of the causes of this may be that the wireload models in the
Synopsys library that you are using are too optimistic.
The tool will then choose smaller, low pin count gates (i.e. mostly
two input) because they are faster than higher pin count gates, at the
expense of increasing the amount of routing required. But since the
wireload model is too optimistic and doesn't take into account the proper
wireload delay, the tools make the wrong choice here.
Now that the tool has increased routing above average, the wireloads will
actually be worse than the norm and what the proper wireload model would
have predicted (a vicious circle!). This results in the high routing
congestion and poor performance of speed critical areas of your design.
- An Anonymous User
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From: epakch@epa.ericsson.se (Kenny Chow - T/HGH)
We released our 21K gates design to Motorola and they ran P&R with
Cadence's Gate Ensemble. It was successful with 'placement.control'
file telling Gate Ensemble to group 12 different groups of circuits
together, without specifying absolute location in the gate array.
We did try imposing the 'tangate.restraints' file onto Gate Ensemble
to specify some critical nets between blocks. Thisattempt failed in
a way that a lot of cells are overlapped after placement. Flattened
netlist is used and the utilization is 68% in the 3-layer metal gate
array. We are still struggling with the post-layout timing.
Hope this can be useful reference information.
Kenny Chow
T/HGH APZ Hardware Design
Ericsson Australia Pty. Ltd.
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From: Martin Lomas <lomasm@computer-science.manchester.ac.uk>
I have seen similar problems with another layout package. The problem
then was that the synthesized design had blocks containing many small
gates (eg 2 input nands) -- Knots of these would be clustered together
by the placement software to reduce routing, and then routing became
impossible due to routing space in those areas being overwhelmed.
The solution? Cell placement constraints to force some of the cells
apart. Messy but a solution. Better would be to get the synthesis tool
to use larger (higher function) cells in the first place rather than
doing lots of low-level function compiling.
(Human designers produced designs with _very_ much lower terminal
counts, giving placement/routing an easier time.)
Sorry, nothing wonderfully useful for you!
(However, I am working on some placement algorithms at the moment.
My software accesses the Cadence design database to get at cell,
netlist and placement info. If you're still struggling nearer to
Christmas, I might be able to help. Sorry but I wouldn't be able
to commit to hard deadlines.)
Martin Lomas, Computer Systems Design
Manchester University, UK
( Post 94 Item 2 ) ------------------------------------------------------
Subject: ESNUG Post 93 Item 3 "Instance names on Synopsys schematics"
>Please can someone tell me how to ask Synopsys to print instance
>names of calls of cell library cells onto the circuit schematic?
From: Ken Lawrence <ken@inmos.co.uk>
Here are a variety of useful commands for Synopsys schematics
set_layer( cell_name_layer, visible, false ) ; /* cell instance */
set_layer( cell_ref_name_layer, visible, true ) ; /* cell type */
set_layer( net_name_layer, visible, false ) ; /* signal name */
set_layer( pin_name_layer, visible, false) ; /* cell connections */
set_layer( osc_name_layer, visible, true ) ; /* off-sheet connections */
set_layer( port_name_layer, visible, true ) ; /* port name */
Cheers,
Ken Lawrence, Inmos Ltd, Bristol, UK.
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