( Post 93 Item 1 ) ------------------------------------------------------
Subject: ESNUG Post 92 Item 3: 'Sum of Products from a "case" statement'
> I'm trying to have synopsys create a simple sum of products
> design from a case statement and not take out the cover terms.
> (It's really an async state machine). I just can't get the tool
> to create this type of simple design. Does anyone have any ideas??
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From: gbrooksh@comanche.ess.harris.com (Greg Brookshire)
We have been told by a synopsys consultant that Synopsys is not
designed to handle asynchronous state machines, YET.
But you might try covering all of the intermediate states in
your case statement. Or, better yet, you could use something
like a one-hot encoding so that there are no intermediate
states that your machine could go through.
These are just ideas. I don't know of anyone at our company
designing asynchronous machines. Our design guidelines strongly
discourage it.
I'd be curious to know of a working solution to this problem.
Good Luck :-)
Greg Brookshire, Harris Corp.
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From: jad@verdin.cdev.com (James A.Dahlberg 490TX)
I'm not sure what you mean by 'cover terms', but if you mean you DON'T
want to create priority encoder logic, then use the parallel_case
directive as follows:
case(condition) // synopsys parallel_case
This makes the case statement generate logic as if all conditions were
"if" conditions and not "else if" conditions. If you want the conditions
prioritized, don't put in this directive.
Jim Dahlberg Computing Devices International
( Post 93 Item 2 ) ------------------------------------------------------
From: hermes@netcom.com (Mark Bonnelycke)
Subject: Mixing Cadence & Synopsys along with routing
Has anyone experienced trouble using Cadence's Gate Ensemble with
Synopsys? We are having trouble with the placement in that it
bunches cells together rather than spread them through the routing
region. The layout engineer has had this trouble on another
synthesized design, and reports that it was solved by re-synthesizing
with another synthesis tool. Our design is large, and has lots of
speed critical areas.
Synopsys, Inc. has suggested that routing difficulty is typical of
these sorts of designs. Does anyone have any ideas or experience
with this sort of problem? Any ideas or suggestions would be
greatly appreciated.
Mark Bonnelycke, Appian Technology
( Post 93 Item 3 ) ------------------------------------------------------
From: Michael Virgo <M.J.Virgo@bnr.co.uk>
Subject: Instance names on Synopsys schematics
Please can someone tell me how to ask Synopsys to print instance
names of calls of cell library cells onto the circuit schematic?
Thanks
Michael Virgo, Bell Northern Research, UK
( Post 93 Networking Section ) -----------------------------------------
ASIC Designer opening : Design ASICs for Telecom applications.
Experience w/ Verilog & Synopsys, 8-10 years in telecommunications
desired. Contact Venkat at (415) 688-2279 or vvankaya@raynet.com
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