( Post 90 Item 1 ) --------------------------------------------------
From: Bob Warren <warrenb@inmos.co.uk>
Subject: Re: Outputs not used for internal feedback. (Post 89 #1)
> In order to "isolate" the timing analysis of the "innards" of a
> particular block from the effects of any output loading, the
> "feedback" must be taken not from the actual output, but from some
> earlier point in the path, even if this means adding an extra
> gate, viz:
>
> /------\
> [>=====|logic | |\
> | |---|>o-+-| >o-------[>
> +---| | | |/
> | | | |
> | \------/ +-|>o----+
> | |
> +---------------------------+
>
> Q: What is the mechanism for persuading the Design Compiler to
> do this?
>
> A: Assuming that you are using a CMOS design, and that timing is
> constrained by "max_transition" and "max_fanout" is redundant
> (which is the norm); use max_fanout in the following manner:
>
> set_max_fanout 100 find(design,"*")
> set_fanout_load 100 all_outputs()
>
>Bob Warren, Inmos Ltd., Bristol, UK.
John,
Please remove my name, address and company. "An Arizona user" would
be fine.
We have a STAR filed with Synopsys:
New variable "internal_use_of_outputs false" or some such name.
Thus, when max_fanout is not redundant the "innards" of a block could
be "isolated" as Bob described.
-- An Arizona user
( Post 90 Item 2 ) --------------------------------------------------
From: [ A mellow Southern Californian ]
Subject: Synopsys' Poor Choice of Asynchronously set/reset Flip-Flops
I ran into this while synthesizing logic using Synopsys' State Machine
Table format (coke machine)...
If you have a design utilizing an asynchronous reset and no asynchronous
set, the design compiler will tend to utilize flip-flops that only
contain reset and no set over those which might be more applicable,
which also contain an asynchronous set (which would be tied low).
For example, we have, in our ASIC library several flip-flops with
asynchronous set and reset which are faster and smaller than the
one flip-flip with mux which has only an asynchronous reset.
If the dont_use attribute is not placed on the flip-flop with mux to
force Synopsys to select the smaller-faster flip-flop, it will use the
flip-flop with mux, tie the first data line low, tie the second data
line to output of the previous logic, and tie the select line to
always select the second data line (!).
-------
1'b0 ------|I0 | ------
previous logic -------|I1 |>-------|D Q|---- output
| Sel | | |
------- CLK --|>clk|
| ------
1'b0 ----'
[ envision it's a single macro of a combined mux & FF
above; (I'm limited by ASCII drawing abilities) ]
Obviously, one can also use the prefered_flip_flip (sic) constraint,
but the Design Compiler should weigh data into flip-flops higher than
whether the flip-flop set/reset matches, exactly, the design logic;
especially if the former is smaller/faster than the latter.
( Post 90 Networking Section ) --------------------------------------------
VLSI opening: Graphics accelerator chip. Experience w/ Verilog & Synopsys.
C & graphics experience desired. Call Don in South Carolina (803) 843-1846.
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