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( Post 88 Item 1 ) -----------------------------------------------------------
From: rbirch@convergent.com (Robert D. Birch)
Subject: problem optimizing of floating inputs (Post 57 Item 1)
> From: bygate@ncrcol.columbiasc.NCR.COM (Terry Bygate)
> Subject: problem optimizing of floating inputs Esnug mailing 52, item #1
>
> The main disadvantage with VHDL is that all states of a FSM...
> ...VHDL does not allow for wild cards/dont_cares.
> As an example,
>
> casex( present_state )
>
> 3'b1xx :
> begin
> ...
> next_state = 7'b101;
> ...
> end
>
> 3'b011 : ...
>
> In VHDL, I believe one would have to list all cases where bit 2 is set
>
> case present_state is
> when "100" | "101" | "110" | "111" =>
> ...
> next_state = "101";
> ...
>
> when "011" =>
> ...
>
> Does anyone have any better ideas how to solve this problem?
We are using Verilog, but before our project started, i spent some time
experimenting with VHDL. If i had a choice, i would use VHDL.
One of the big features of VHDL is overloading operators.
i was using the 1164 logic package, so i redefined a new set of operators
for std_logic, similar to what is done in arithmetic.vhd in the Synopsys
hierarchy. i made the relational operators ignore signal strengths and
dont-cares.
That way, even though "case" does not understand X's the way we may like,
the same thing could be accomplished with:
if ( present_state = "1--" ) then
...
next_state <= "101";
...
else if ( present_state = "011" ) then
...
One thing to watch out for... the relational operators are implicitly defined
for enumerated types when the type is defined. That means that if you are
using package std_logic_1164, which contains an implicit definition for "=",
and you are also using a package std_logic_ops, which contains your new and
improved version of "=", then two versions of "=" will be visible for type
std_logic, which is illegal.
Solutions:
1) define a new type, and define the new operators in the same package
(this is what is done in arithmetic.vhd).
2) define the new "=" function inside the archtecture where it is to be used.
3) Instead of the "=" operator, define new boolean function such as
if ( equal(present_state, "1--") ) then ...
(You lose infix notation with this solution, though.)
By the way, the Synopsys installation has an option to define your default
vector type as SIGNED or UNSIGNED. If neither of these is chosen, the
package arithmetic.vhd defines SIGNED and UNSIGNED as new array types.
If one of them is chosen as the default, however, then that default is
declared as a subtype of your bit vector, eg.
subtype SIGNED is std_logic_vector;
The result is the above problem with two visible defintions of "=" for
std_logic_vector. This is accepted by Design_Compiler, but it is a violation
of 1076, and is illegal in a compliant simulator. (i mentioned it to the
hotline folks, and also to our instructor during a class at Synopsys, but
i see the feature has still survived in version 2.2b).
Robert D. Birch
Unisys, San Jose
rbirch@convergent.com
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