ADMIN NOTE: Because ESNUG was living on a system that's used to test new
operating systems, it was equivalent to living in e-mail Beruit! ( I've
had more than a few people send me ESNUG contributions only to later find
that they didn't make it to me and they didn't bounce back - they just
disappeared!) Finding this to be too crazy, I've moved ESUNG to:
"jcooley@world.std.com"
Sorry for the foobars. :^( - John
( Post 87 Item 1 ) --------------------------------------------------------
From: msprague@sequoia.com (Mark Sprague)
Subject: Non-informative Timing Reports Through Hierarchy
In rev 2.2b, there is a fairly significant bug with normal -path full
(non-flat) timing reports in a hierarchical design. In some cases, the
entire path will not be reported, but the timing will be correct. This
has been assigned STAR 7565. To illustrate this, consider the following
-path full timing report without a corresponding "-flat".
pg/v_d[1] d_pg 1 40.82 f 40.82
glue_2/dpm_control_q_reg[1]/D DFFSCAN 1 46.46 r 5.64
The same path reported with a "-flat":
int_bus_in[27] in 2 20.00 f 20.00
glue_int/U325/X AND2H 1 20.76 f 0.76
glue_int/U322/X NOR8H 1 22.75 r 1.99
glue_int/U343/X INV2B 33 26.37 f 3.62
pg/U273/X EXOR3H 1 29.65 f 3.28
pg/U270/X INV2B 1 30.12 r 0.47
pg/U533/X EXNORA 1 31.29 f 1.17
pg/U531/XB MUX2IH 2 32.81 r 1.52
pg/U338/X EXNORA 1 34.20 r 1.40
pg/U314/X INV2B 2 34.83 f 0.62
pg/U401/X EXORA 1 36.14 r 1.32
pg/U245/X INV2B 5 37.08 f 0.94
pg/U405/X NAN2H 2 38.06 r 0.98
pg/U563/X OAI211 1 39.19 f 1.13
pg/U350/X NAN2H 1 40.23 r 1.03
pg/U351/X INV2B 3 40.82 f 0.59
glue_2/U66/X MUX2A 1 41.94 f 1.12
glue_2/U36/X OR3 1 43.56 f 1.63
glue_2/U38/X NAN2 1 44.94 r 1.37
glue_2/U40/X EXNORA 1 46.45 r 1.52
glue_2/dpm_control_q_reg[1]/D DFFSCAN 1 46.46 r 0.00
Missing from the top report is an entry for int_bus_in, and the port
connected to glue_int/U343/X. The top timing report should look like:
int_bus_in[27] in 2 20.00 f 20.00
glue_int/int_bus[27] d_glue_int 33 26.37 f 6.37
pg/v_d[1] d_pg 1 40.82 f 40.82
glue_2/dpm_control_q_reg[1]/D DFFSCAN 1 46.46 r 5.64
[Editor's Note: Mark's saying something to the effect of:] "That is, the top
timing report that was not "-flat" should have shown the intermediate modules
"glue_int" -> "pg" -> "glue_2" with their contributing delays to the overall
path instead of just having pv/v_d[1] magically appear at time 40.82!"
The method used to create this model is to compile each module seperately,
and write out a synopsys data base for each of these modules. Once all
modules have been compiled, the data bases are read back in, linked, and
the timing reports are generated. This feature appears in hierarchical
designs of both 6000, and 50k gates, so it doesn't appear to be a size
restriction.
While synopsys is generating the correct total timing, the usefulness of
the non-flat report is limited by this feature. This will be fixed in some
future rev. The workaround in the mean time is to generate a flat timing
report, and use grep or an editor to look up the corresponding net names.
An enhancement request has been filed to add a switch to the -path full
-flat timing reports that will automatically insert the driven net, instead
of the driving pin. This is STAR 7566.
( Post 87 Networking Section ) --------------------------------------------
Howard Landman, formally "landman@xpoint.com", is pleased to announce that
he has joined HaL Computer Systems and may be reached at: "landman@hal.com".
VLSI DESIGN JOB OPENING: Microprocessor peripheral design. Must have 3-5years
experience using Verilog HDL and Synopsys. DRAM controller & 68040 helpful.
AT: Motorola, Phoenix, AZ. CONTACT: davidf@digital.sps.mot.com (602)962-3329.
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