( Post 86 Item 1 ) ---------------------------------------------------------
From: cindy@en44.zoran.hellnet.org (Cindy Eisner)
Subject: synopsys tri-state bug
hi john,
here is a synopsys bug for the next esnug:
version: 2.2b.
if you have a hierarchical model in which the child model contains a
tri-state buffer which drives a large load, synopsys will sometimes
"solve" the load by adding inverters after the tri-state buffer in
the instantiating model.
definition of "sometimes": if this particular block declares the
tri-state as "output".
workaround: declare every tri-state as "inout", even if it only drives
the bus.
warning: this bug is very hard to detect, since your block simulations
will run fine. it is only on full-chip simulations that the bug will
manifest itself. in addition to using the workaround, we have a script
that checks that no tri-state signal is driven by something other than
a tri-state buffer.
cindy.
Cindy Eisner CAD group, Zoran Microelectronics LTD
Advanced Technology Center Haifa 31204, Israel
( Post 86 Item 2 ) ---------------------------------------------------------
From: Bob Warren <warrenb@inmos.co.uk>
Subject: ESNUG DC 2.2b Case sensitivity in records
John,
The Design Compiler 2.2b is case sensitive to the field descriptors of
records when reading VHDL and crashes with a
"Fatal: Internal system error, cannot recover."
if the case is incorrect. No other information is given, so unless
you know about this, you are hard pressed to find out what went wrong.
TYPE my_record_t IS RECORD
CaseSensitive : mvl7;
END RECORD
SIGNAL my_record : my_record_t;
SIGNAL my_signal : mvl7;
my_signal <= my_record.CaseSensitive -- passes
my_signal <= my_record.casesensitive -- fails
WARNING: If records are used in VHDL, retain the case of the field descriptors.
Bob Warren, Inmos Ltd., Bristol, UK.
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