( Post 85 Item 1 ) ------------------------------------------------------
From: jgais@wd.estec.esa.nl ( J.Gaisler )
Subject: paranthesis bug ( Post 78 Item 2 )
> Jiri, your contribution begs the question of: "Exactly what are you
> using as "some_signal" when you see this problem ? Is it an individual
> signal?, a vector?, a constant?, a complex expression?" -John
OK, here is the clarification of the Synopsys paranthesis bug (?) :
If the first CASE statement is accepted the the second one should be
accepted as well...
Regards, Jiri Gaisler
- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X-Sun-Data-Type: default
X-Sun-Data-Name: test.vhd
X-Sun-Content-Lines: 32
entity dummy is
end dummy;
architecture BEHAVIORAL of dummy is
BEGIN
Process
SUBTYPE BV2 IS Bit_Vector(0 TO 1);
VARIABLE Tmp : Bit_Vector(0 TO 1);
BEGIN
CASE Tmp IS -- Passes
WHEN "00" => Null;
WHEN Others => Null;
END CASE;
CASE (Tmp) IS -- Fails
WHEN "00" => Null;
WHEN Others => Null;
END CASE;
CASE Bit_Vector'(Tmp) IS -- Fails
WHEN "00" => Null;
WHEN Others => Null;
END CASE;
CASE BV2'(Tmp) IS -- Passes
WHEN "00" => Null;
WHEN Others => Null;
END CASE;
END Process;
end BEHAVIORAL;
( Post 85 Item 2 ) ------------------------------------------------------
From: Bob Warren <warrenb@inmos.co.uk>
Subject: vhdl_strict variable
(From Post 81 Item 2):
> Here's a little tip if you're finding you're running out of
> memory space when you're running Synopsys. Before you read,
> write or compile anything, put early on in your script:
>
> perserve_subshells = {}
John,
This is the very sort of thing I need to know!
Perhaps there are some tricks which I am using which may be of benefit to
others. For example, do you know about:
vhdl_strict = false
to stop the VSS parser from reporting a load of rubbish when reading in
VHLD into the DC?
The vhdl_strict "variable" is "NOT supported", in that it could vanish in
future releases, but is present in the Design Compiler 2.2b. A "read -f vhdl"
proceeds, as described in the manuals, by first using the VSS parser as a
syntax checker, and then loading the VHDL into the DC database. For each
"library" that is read from the source VHDL, the VSS parser generates messages
of the following form:
/<full_path_details>/ctrlsys/ctrlsys.vhd:
USE ims_prim_lib.prim_types.ALL;
Warning: (VHDL-10998) line 5
Design library management is NOT supported for synthesis. Mapping library
"IMS_PRIM_LIB" to "WORK".
When vhdl_strict is set to false, errors in the VSS parser phase are ignored,
and some of the messages are omitted.
Using vhdl_strict=false can be used as a work around when VSS parser gets into
a knot with the VHDL, particularly with libraries, and it produces a slightly
cleaner log file.
Bob Warren, Inmos Ltd., Bristol, UK.
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