( Post 83 Item 1 ) -----------------------------------------------------
From: [ An East Coast Synopsys User ]
Subject: Scan & Motorola's CMOS H4C Synopsys Library & a Bug!
jcooley@sequoia.com writes:
> job better. It may not be as exciting as reporting a real nastey
> bug you've found, but I think these methodologies are just as helpful
> to the Synopsys user. Keep sending them in!
> -John
Along those lines, I'm adding the following. Please no name, company, etc.
We're using Synopsys' register inferencing capability in our design's
behavioral Verilog code to keep things technology independent.
In order to incorporate scan functionality into our designs, we've
found that the best methodology that we've come up with so far goes
along the lines of:
1) Write the design in Verilog behavioral form with
no direct instantiating of any technology dependent macros.
2) Run the Verilog code through Synopsys to get a gate level
version of the design that meets timing and area constraints.
(Important: infer only the simplest, most basic flip-flop
from the library you're using. Preferably, a flip-flop
that only has a "D", "Q" and a clock. Use the Synopsys
command "set_default_flip_flop_type -exact" to insure that
you're getting only that one simple flip-flop in your design.)
3) Run the gate level design through a post-processor to replace
the simple flip-flops with scan flip-flops while hooking up
a scan chain throught the design.
(A lot of people doing scan use post processors. :^) )
Our problem with the Motorala CMOS H4C Synopsys library is that there's
no simple flip-flop that we can use as a basic building block in step 2!
Every flip-flop either has a "Q" with a "QB" ( inverted "Q" ) or, in
the case of the scan flops, a "Q" with a "QS" ( scan "Q" ).
What happens is that the design compiler in Synopsys uses both the "Q"
and the "QB" (or the "QS") outputs in driving the logic within the
design - which royally messes up our trying to do step 3!
The workaround that we've finally settled on is that we've added
a "simple" flip-flop to our copy of the Motorola H4C library. (Of
course, not everyone has access to a Synopsys Library Compiler; what
they're to do, I don't know.)
If I could think of a functionality that would be nice for Synopsys
to add to there tool set, it would be a command the user could put
on specific macros in their technology library that's something like:
dont_use_library_macro_pin "DFFLPB/QS"
That way, I could have used any of the H4C scan macros but disabled
Synopsys from using the "QS" pin to drive logic and my design post
processor would only have to hook up the scan chain!
P.S. If you're going through the trouble of recompiling the Motorola
H4C CMOS library, you may want to add functionality to the TREEBUF2,
TREEBUF3, TREEBUF4 and TREEBUF5 macros. Because it's accidently
missing, Synopsys picks the worst timing arc it can find in the
library (Good!) but chooses seemingly random functionality - sometimes
in the Synopsys timing reports signals going through these non-functional
macros become inverted, sometimes not. (Bad!)
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