Reminder: If you're having trouble sending e-mail to: "jcooley@sequoia.com",
try e-mailing to: "jcooley@miracle.com" (My system's been flakey lately.)
( Post 82 Item 1 ) --------------------------------------------------------
From: "Elliot H. Mednick" <elliot@wellspring.com>
Subject: Open Verilog International's Call for Papers
There are still some openings for papers for the next Open Verilog
International (OVI) Conference in March. Many good papers have already been
received, but, interestingly enough, there have been very few submissions
on the topic of using Verilog for synthesis and with some of the
nuts-and-bolts ASIC issues, such as clocking, design-for-test, and scan.
Most of the readers of ESNUG have a great deal of experience in these
topics. (I keep back issues as evidence! :-). Presenting a paper is not
all that difficult, and you will be helping lots of other Verilog
users. Also, it will look great on your resume! If you still
remember your learning curve, you can empathize with others who are
about to go through the same thing.
If you would like to share your experiences, guidelines, techniques,
etc., send me some e-mail and we'll work out an abstract. Better yet,
if you already have an abstract, e-mail it to me at <elliot@wellspring.com>.
If you have some doubts, but consider yourself an expert, send me
e-mail anyway and I'll talk you into it :-)
Thanks for your attention.
-Elliot
P.S In case you were wondering: yes, I am on the OVI Program Committee;
No, I am not a member of OVI (but I sit in on a bunch of committees);
No, my company doesn't compete with your company -- we're just another
Verilog clone vendor; Yes, I presented a paper last year -- made me
famous.
( Post 82 Item 2 ) --------------------------------------------------------
From: jaa@SU59D.ess.harris.com (John Auer)
Subject: RE: Synopsys does not understand invalid gate input states
>> jaa@mongoose.ess.harris.com (john auer) writes:
>>
>> Did Synopsys have any trouble making the synthetic library? (install_synlib)
>> In my experience, "unable to map" reflects an out-of-date synthetic library
>> (library.mod file). Just a thought...
> cindy@ca45.zoran.hellnet.org (Cindy Eisner) writes:
>
> sorry i did not make myself clear here. what i meant was that when i
> defined a tri-state buffer with inputs required to be opposite, using
> the pin_opposite attribute, i got the "unable to map" error message.
> otherwise, the tri-state buffers were mapped fine.
jaa@mongoose.ess.harris.com (john auer) writes:
Agreed, I was able to reproduce this behavior in VHDL. Something is
broken. I'll report this as a bug. In the final analysis, however,
this is a different bug than the one I originally reported. This "new"
bug is a breakdown in the synthesis process. The original bug concerned
Synopsys not understanding that certain inputs MUST always be opposites
of one another. This lack of knowledge on the tool's part causes a
breakdown in both the optimization and synthesis processes;
non-complimentary logic will be synthesized, and complimentary logic
(from non-HDL sources) is sometimes optimized into a non-complimentary
result.
Even when Synopsys fixes the "unable to map" bug, the original problem
will remain--complimentary logic will be synthesized, but optimization
will result in a non-complimentary result.
John Auer
Harris GASD
jaa@mongoose.ess.harris.com
OK to use name
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