( Post 80 Item 1) ----------------------------------------------------------
From: brier@e5sb.osdhw.syr.ge.com (brier)
Subject: Synopsys & Vantage's VHDL Incompatabilities
Along the lines of Mark Gonzales' Post 79 Item 1, we've some VHDL issues, too!
Here are a couple of incompatabilities that we have found in using Synopsys and
Vantage VHDL products.
(For those of you who are used to working in Verilog, you'll find in VHDL
that everything must be declared as opposed to what one is used to doing in
Verilog. Bug # 1 is an example of all the typing that must be done in
VHDL. The first part is the original type declaration, the second is
bundling it into a record (signal bundle) so you can use it.)
1. Type declarations being used to type a record, then being used within that
record elsewhere in the code.
These are declarations in package "commmon_package":
type UNIT_ID_TYPE is (H32, X1, X2, X3, X4, X5, X6);
type PBOWN_TYPE is (H32, EXT); -- P12(i960) or EXTernal owns bus
Later there is a declaration of a record using the above types an
E/A pair.
type MONITOR_BUS_TYPE is record
UNIT_ID : UNIT_ID_TYPE;
TIME_TAG : TIME;
INSTRUCTION: READ_WRITE_TYPE;
ADDRESS : STD_LOGIC_VECTOR(31 DOWNTO 0);-- ADDRESS/DATA
DATA : DATA_TYPE;
WORD_COUNT: WORD_COUNT_TYPE;
end record;
The following failed during compilation in Synopsys, but was OK in
Vantage where the signal assignment is made for the H32 variable in
architecture test_a.vhdl.
MONITOR_BUS : out MONITOR_BUS_TYPE :=
( UNIT_ID => H32,
TIME_TAG => 0 ns,
INSTRUCTION => NOP,
.
.
.
This has been reported to Synopsys, but I haven't received any
resolution.
2. When a signal is passed through to a proceedure, but not through the calling
declaration ( i.e. procedure dog (a, b, c).... and the value d is in the
calling code, but used within dog. First it is visible, and secondly you
would assume that section 4.3.3 of the LRM would apply. Well Vantage looks
at this as prohibiting attributes as discussed in 4.3.3, but Synopsys allows
attributes. I have received an explanation from both, and it looks as
though the LRM is ambiguous.
example: wait until (d'delayed = '1' and rising_edge(clk));
This fails in Vantage but is OK in Synopsys.
3. Another issue is that in some situations Synopsys is more demanding and
requires type casting more often than Vantage. We have developed code that
will work in Vantage only to be required to type cast the same relational
expressions to have them work in Synopsys.
Most of these issues are not major show stoppers, the root is that it appears
for the near future, that there will be differences in the way the LRM is
implemented by each vendor. It could be worse, there are other VHDL simulators
that would not fit nearly as well.
VHDL is FUNNNN !
Dave Brier
GE Syracuse
brier@e5sb.osdhw.syr.ge.com
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