ADMIN NOTE: In the past 7 days, if you've sent something for ESNUG and have not
received a reply, please resend it. My system went through an "upgrade" that
effectively caused it to throw away or bounce back 90% of incoming e-mail.
Since I was receiving some incoming mail, it took a few days to discover this
problem and then it's taken a few more days to fix it. The problem seems to
have been corrected now.
IN THE FUTURE: If you have not received any acknowledgement or are getting
bounce backs of something you've sent for ESNUG at "jcooley@sequoia.com", please
try "jcooley@sequoia.sequoia.com". If that fails, please send the error
message plus your ESNUG contribution to a backup account: "jcooley@miracle.com".
Sorry for the SNAFU. -John
( Post 77 Item 1 ) ------------------------------------------------------------
From: cindy@ca45.zoran.hellnet.org (Cindy Eisner)
Subject: Re: Post 75 Item 2
> From: d_pinvidic@emulex.com (Dan Pinvidic)
> Subject: Question for ESNUG group
>
> Question: Can a verilog description of a 2-1 mux which has one data
> input grounded get mapped to a 2-1 mux from the library. All efforts result
> in a nor gate controlling EMO. EMO and FMO must have matched path delays...
well, MUST you have a mux, or is the real problem that they must have matched
path delays? if you can tolerate non-muxed logic as long as the path delays
are matched, then use "min_delay" in conjunction with "max_delay" on the
two outputs to get them as close as you want.
Cindy Eisner, CAD group, Zoran Microelectronics LTD
Advanced Technology Center, Haifa 31204, Israel
( Post 77 Item 2 ) ------------------------------------------------------------
[ Editor's Note: from a laid back Californian who wishes to remain anonymous]
Subject: Re: ESNUG Posting Number 76 Item 1
I ran into this problem about a year ago & told Synopsys. Here is the fix which
Synopsys recommends for Howard's problem. (I've translated it into terms of his
library.) I've found this solution to be quite effective but it's the library
developer must supply this change, it cannot be implemented in the field without
the user having the Library Compiler:
The target library contains only a FF with both set and clear:
cell(TEST_FDP1B) {
state("IQ0","IQN0") {
next_state : "D" ;
clocked_on : "CK" ;
force_01 : "!CDN" ;
force_10 : "CDN !SDN" ;
force_00 : "CDN SDN" ; <- defines the "undefined" state, and
causes synthesis to work properly.
}
pin(D) {
direction : input ;
}
pin(CK) {
direction : input ;
}
pin(CDN) {
direction : input ;
}
pin(SDN) {
direction : input ;
}
pin(Q) {
direction : output ;
function : "IQ0" ;
}
}
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