( Post 73 Item 1 ) ----------------------------------------------------------
From: trevor@ncd.com (Trevor Pearman)
Bug Alert
---------
Tool: Synthesis
Input: VHDL
Output: Produces wrong logic
Confirmed: by Synopsys
Fix: maybe in 3.0?
Description:
I have found a bug in the synthesizer with regard to VHDL records with more
than 2 levels and arrays.
With records that are nested more than 2 levels and have arrays; the indexing
operation does not work correctly. There are no errors or warnings; only bad
logic.
Work around:
Move the array to a temporary variable before attempting to index into it.
Example:
type T_A_5_int is array(0 to 5) of integer;
type T_5_PLUS_1_INT is record
X: integer;
Y: T_A_5_int;
end record;
type T_5_PLUS_1_PLUS_1_INT is record
X: integer;
Y: T_5_PLUS_1_INT;
end record;
type T_FOO is record
X: integer;
Y: T_5_PLUS_1_PLUS_1_INT;
end record;
...
signal RECORD_INTS: T_FOO;
signal BAD_VALUE: integer;
signal SELECT: integer;
....
BAD_VALUE <= RECORD_INTS.Y.Y.Y(SELECT);
....
-- Trevor Pearman trevor@ncd.com
-- Network Computing Devices Inc
( Post 73 Networking Section ) -----------------------------------------------
From: fields@danube.acuson.com (Julian Fields)
Synopsys, Verilog, spice, LSI Logic, Mentor Graphics, Unix, Compass Tools, and
VLSI design engineer (for 12 yrs) looking for contract opening. (408) 773-8197
|
|
