ADMIN NOTE: Post 72 may be coming to some of you twice due to a reset
on my local network sometime last night. - John
( Post 72 Item 1) ---------------------------------------------------------
From: epakch@epa.ericsson.se (Kenny Chow)
Subject: Post 71 Item 1
Lee, Your question misses some details and I would like to ask more and
give some conditional comments.
If you are using CASE statement (VERILOG) to build the combinational part
of the state machine, be sure to use comment '//Synopsys full_case
parallel_case'. One possibility is you have 'default' definition, or you
don't have the 'full' and 'parallel' Synopsys directive and it will generate
circuit to take care of the undefined encoding state. These redundant
circuits may provide propagation path for unknowns.
A side question is do you see the unknown propagate through the gate level
circuit or through the model ? I suppose only the gate level circuit.
- Kenny Chow, Ericsson Australia. (OK to use name and company).
( Post 72 Item 2) ---------------------------------------------------------
From: brucel@zulu.sps.mot.com (Bruce A. Loyer-Highend Comm)
Subject: Post 71 Item 2
To: John Spillane, Data General
I have worked out a method to transfer schematics from synopsys to Cadence
Analog Artist. I suspect it will also work for you. First of all, you must
set the edifout switches in synopsys. The ones that I use are:
edifout_power_and_ground_representation = "cell"
edifout_ground_pin_name = "P1"
edifout_ground_name = "GNDTIE"
edifout_power_name = "VDDTIE"
edifout_power_pin_name = "P1"
edifout_external = "true"
edifout_netlist_only = "false";
edifout_pin_direction_in_value = "in";
edifout_pin_direction_inout_value = "inout";
edifout_pin_direction_out_value = "out";
edifout_pin_direction_property_name = "";
edifout_skip_port_implementations = "false";
edifout_instantiate_ports = "true"
In addition, the default settings (which are overwritten by the ones above) are:
edifout_dc_script_flag = "";
edifout_design_name = "";
edifout_match_vhdl_names = "false";
edifout_top_level_symbol = "true";
edifout_unused_property_value = "";
edifout_write_attributes = "false";
edifout_write_constraints = "false";
edifout_write_properties_list = {};
Then, I had to modify my symbol library to match Cadence requirements for
set_route_grid and set_meter_scale. Below is an example. Synopsys would fail
if one of the libraries had a different meter_scale or route_grid from the
other. I don't remember if the error message was exactly as you have but it
sounds familar. This was a problem because I was also using the generic library
for off sheet connectors, etc. I had to create a special symbol library for
this also. We use a symbol library from Valid which allows us (somewhat) to go
back and forth between synopsys and valid schematic capture. This must be
modified to tell synopsys which symbol to use for a bus ripper. To that symbol,
add the following lines:
ripped_pin : B; /* capalization counts!! */
ripped_bits_property : BN;
Then you need to add some general lines to tell synopsys to use this library.
These go outside of the symbols but within the library definition.
/* special symbol name declarations */
logic_1_symbol : VDD;
logic_0_symbol : GND;
in_port_symbol : SYNOPINPORT;
out_port_symbol : SYNOPOUTPORT;
inout_port_symbol : SYNOPINOUT;
in_osc_symbol : SYNOPINOSC;
out_osc_symbol : SYNOPOUTOSC;
inout_osc_symbol : SYNOPINOUTOSC;
} /* end of library "SYNOP.LIB" */
Here is the start of my special library. Please note: Even though I got
everything to work using just my special libraries, synopsys still will give
you the message that it is loading the generic library. This is all right
as long as it does not use it.
library("special") {
SCALE = 1.0 / 60.0;
ROUTE_GRID = 10;
set_route_grid(ROUTE_GRID);
set_meter_scale(0.0254 / (480 * SCALE * ROUTE_GRID));
symbol("AND2") {
set_minimum_boundary(-180 * SCALE, -240 * SCALE, 384 * SCALE, 204 * SCALE);
line(60 * SCALE, 156 * SCALE, 216 * SCALE, 156 * SCALE);
line(216 * SCALE, -36 * SCALE, 60 * SCALE, -36 * SCALE);
line(60 * SCALE, -36 * SCALE, 60 * SCALE, 156 * SCALE);
line(0 * SCALE, 120 * SCALE, 60 * SCALE, 120 * SCALE);
line(0 * SCALE, 0 * SCALE, 60 * SCALE, 0 * SCALE);
line(300 * SCALE, 60 * SCALE, 360 * SCALE, 60 * SCALE);
line(48 * SCALE, 132 * SCALE, 48 * SCALE, 108 * SCALE);
arc(216 * SCALE, 156 * SCALE, 216 * SCALE, -36 * SCALE,\
203.143 * SCALE, 60 * SCALE);
pin("X", 360 * SCALE, 60 * SCALE, ANY_ROTATION);
pin("B", 0 * SCALE, 0 * SCALE, ANY_ROTATION);
pin("A", 0 * SCALE, 120 * SCALE, ANY_ROTATION);
} /* end of symbol "AND2" */
} /* end of library "special" */
I hope this helps. Obviously, in order to use this solution, you need the
library compiler.
Bruce A. Loyer
Motorola
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