ESNUG returns! - after a two week vacation "due to technical difficulties",
Synopsys users can once again get down to the business of trading horror
stories and/or techniques on how to get the most out of their Synopsys tools!
Sorry for the delay; but these things happen! - John Cooley
( Post 71 Item 1 ) ---------------------------------------------------------
From: lee.bradshaw@clemsonsc.ncr.com (Lee Bradshaw)
I have a question about unknowns feeding into state machines.
simple example:
state0: if a then state1
state1: if b then do something
else state0
The signal b will always be valid one clock after a is true, but how do you
tell the state machine to ignore the value on b except in state1. My circuits
usually have more states and b is asychronous to the clock, although it meets
setup and hold requirements for state1. I generally instantiate an and gate
to block b except in state1, but this hurts design portability and prevents
the best optimization.
Does anyone else have this problem? Is there another solution? Could
synopsys have a compiler option to specify a special type of signal?
Thanks,
lee.bradshaw@clemsonsc.ncr.com
( Post 71 Item 2 ) ---------------------------------------------------------
From: johns@emavp22.webo.dg.com (John Spillane)
I am trying to write out an edif file from 2.2b to use as input to
Cadnece's Composer schematic capture system. I had to create symbol
libraries from Composer so that the scales match. The problem is that
i get "Error: Write command failed. (UID-25)" when i try to do this.
This error message is so general I haven't a clue of where to start
looking for a solution. Has anyone run into a similar problem when
writing edif files.
John Spillane
Data General
( Post 71 Item 3 ) ---------------------------------------------------------
From: victor%boiler@uunet.UU.NET (Victor J. Duvanenko)
The Synopsys schematic capture needs quite a bit of help before it becomes
a real 'production-level' product. Presently, it can not do any bus-ripper
type stuff - such as a bus tap that is a bus itself, it does not do type
checking of VHDL types when you perform the ERC check. And it has many
quirks when it comes to the user interface.
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