( Post 66 Item 1 ) -----------------------------------------------------
From: roberts@slc.unisys.com (Doug Roberts)
Here's another item.
There is a great weakness in the synthesis process, at least on the Mentor
workstation.
It is that the Mentor interface can not handle busses.
We have a design here that had about a 100 nets that were part of various
busses. We were able, with some effort, to create and interconnect the
busses in the Synopsys schematic editor (see my previous submission). We
ran a successful simulation. Then when we went to create Mentor "do" files
for the NetEd editor, the interface could not handle busses.
So the schematics we ended up with in NetEd have huge symbols with many nets.
To make them readable, we are having to manually create busses and new
symbols and schematics in Neted. I hope we don't make a connect error.
It seems at times that the whole Synopsys synthesis process is redundant.
We end up creating schematics and simulating twice. I hope they fix the
interface (by adding bus capability) quickly.
( Post 66 Item 2 ) -----------------------------------------------------
From: Paul Micheletti 3774 <pm1@ws081.torreypinesca.NCR.COM>
Continuing the fray about Synopsys and unknowns:
authors: Paul Micheletti <pm1@ws081.torreypinesca.NCR.COM>
Cindy Eisner <cindy@Zoran.HellNet.Org>
Michael Parkin <parkin@ultrasparc.Eng.Sun.COM>
paul> Most gate-level simulators will produce a behavior different from the
paul> one described above. If Synopsys generates logic where the (synchronous)
paul> RESET signal sets both inputs to a multiplexer to the same value, but
paul> the select line for this mux is not gated with RESET (thus unknown upon
paul> initialization), then the output of this mux will be unknown in most gate
paul> level simulators.
cindy> no, i do not agree. this is not a function of the simulator but rather
cindy> a function of the simulation library. this is something that you can
cindy> control easily in all simulators that i am familiar with, and modeling
cindy> muxes as parkin@ultrasparc.Eng.Sun.COM (Michael Parkin) suggests:
michael> If "a" is unknown and (in0 == in1) the return value should be
michael> known. Muxes should be modeled in this way so that the
michael> gate-level logic simulates correctly, otherwise some flip-flops
michael> will not reset.
cindy> is well worth your time. model a mux correctly and you save endless
cindy> tweaking of the syntheses or hdl code.
Unfortunately, when working with an ASIC vendors "golden" gate-level simulator,
you don't always have the ability to tweak on simulation libraries. At this
plant we have used two different ASIC vendors, and both of them have
encountered this problem of propogating resets all the way to the flip-flops.
One of the vendors (I'm not naming names) had a sign-off simulator that ran on
Valid, allowing us access to the simulation libraries. The other vendor used a
proprietary simulator that we were unable to touch since the signoff
procedures require that all test vectors run perfectly on an un-altered
simulator.
Again, I must assert that this is a Synopsys bug. Instead of requiring every
simulation model vendor (and/or user) on earth to write simulation models that
will make Synopsys happy, Synopsys should allow the user to specify that a
particular signal is used for synchronous reset, and should respect the users
wishes by not generating unsimulatable logic.
Paul Micheletti <pm1@ws081.torreypinesca.NCR.COM>
|
|
