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i finally decided to join the fray regarding synopsys and unknowns. as always,
it is fine to use my name, company name and other information.
cindy.
Cindy Eisner, CAD group,
Zoran Microelectronics LTD, E-mail: cindy@Zoran.HellNet.Org
Paul Micheletti 3774 <pm1@ws081.torreypinesca.NCR.COM> writes:
> Most gate-level simulators will produce a behavior different from the
> one described above. If Synopsys generates logic where the (synchronous)
> RESET signal sets both inputs to a multiplexer to the same value, but
> the select line for this mux is not gated with RESET (thus unknown upon
> initialization), then the output of this mux will be unknown in most gate
> level simulators.
no, i do not agree. this is not a function of the simulator but rather a
function of the simulation library. this is something that you can control
easily in all simulators that i am familiar with, and modeling muxes as
parkin@ultrasparc.Eng.Sun.COM (Michael Parkin) suggests:
> If "a" is unknown and (in0 == in1) the return value should be
> known. Muxes should be modeled in this way so that the
> gate-level logic simulates correctly, otherwise some flip-flops
> will not reset.
is well worth your time. model a mux correctly and you save endless tweaking
of the syntheses or hdl code.
victor@truevision.com (Victor J. Duvanenko) writes:
> I was unfortunate enough to be the first to discover the 'synthesizable-but-
> unsimulatable' bug. This came very late in the design cycle as well, to make
> things even worse. The trouble with synthesis in general is that the
> synthesizer treats logic in terms of a truth-table, and then finds an
> implementation that will have an equivalent functionality. The logic that
> the synthesizer generates will work in real life, since every node will be
> a 1 or a 0 (since there is no such logic state as a X). But, the simulators
> start up with all nodes being at X, and can't deal with another node being
> (not X). If simulators could actually keep track of node A being X, and node
> B being (not node A) then the synthesized logic would work fine. But, most
> simulators don't keep track of node-to-node relationships - they simply say
> (not X equals X).
this is another matter, and i have not yet seen it. out of curiousity, would
you be willing to share some hdl code and resulting gate level implementation
that illustrates this problem?
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