( Post 64 Item 1 ) ---------------------------------------------------------------
From: jaa@mongoose.ess.harris.com
Subject: Post 62 Item 1 & Post 63 Item 2
> cindy@ca45.zoran.hellnet.org (Cindy Eisner) writes:
>
> very strange. in the library compiler (cmos) reference manual, version 2.2,
> page 5-10, you can find the "pin_equal" and "pin_opposite" attributes, which
> as described, should do what you want. i tried creating a tri-state buffer
> as you describe and it compiles fine under the library compile. however,
> a compile of a simple verilog design gives the following:
> Information: Unable to map three-state cells. (OPT-125)
> Information: Leaving generic three-state cells in design. (OPT-126)
> so: this is definitely a bug and not an enhancement request. i'll leave
> it to you (John Auer) to update Synopsys.
For this problem, pin_equal and pin_opposite have no effect (Synopsys
confirmed this when I first ran into this problem). Pin_equal/opposite
statements seem to be used by Synopsys only if the equations for the
function of the gate and/or three_state are not given; otherwise,
Synopsys deduces them from the equations.
I don't use verilog, and I haven't seen a similar mapping problem with
VHDL. I ran a test case on a VHDL tristate design today without incident.
The problem as originally reported to Synopsys is accurate, so I will not
be upgrading the STAR to a bug.
Did Synopsys have any trouble making the synthetic library? (install_synlib)
In my experience, "unable to map" reflects an out-of-date synthetic library
(library.mod file). Just a thought...
John Auer
Harris GASD
jaa@mongoose.ess.harris.com
(OK to use name)
( Post 64 Item 2 ) ---------------------------------------------------------------
I have been using Synopsys for some months and I am currently trying to
use the Genrad simulator (HILO 4 environment) to functionaly simulate
VHDL code.
First I run my VHDL code through the Synopsys VHDL compiler and if OK then
would like to functionaly simulate the circuit with the Genrad simulator
without having to rewrite my VHDL code.
So far I have to change my source (Synopsys) VHDL code befor I can use
Genrad.
Has anyone any experience with both environments?
How do you use the tools?
I would like to hear it from you.
Many thanks
Alain Rabaeijs
Imec vzw
mail address : rabaeijs@imec.be
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