( Post 63 Item # 1 ) ---------------------------------------------------
From: roberts@slc.unisys.com (Doug Roberts)
Here's a new gotcha for you.
In the Synopsys schematic editor, if you create two busses, with different
names, say A and B, and you use bus taps and try to connect, say, A(3) to
B(3), it won't let you, because the net names are different. Well, maybe
that is what you want, but there is no neat workaround. In NetEd, the
Mentor schematic editor, there is a "buscon" connector to allow you
to connect differently named nets. Synopsys does not have such a simple
device.
I ended up creating a new module, then coding the connections in VHDL.
I called hotline on the problem, and they admitted that they have no
easy way to do this.
( Post 63 Item # 2 ) ---------------------------------------------------
From: cindy@ca45.zoran.hellnet.org (Cindy Eisner)
Subject: Post 62 Item 1
jaa@mongoose.ess.harris.com (John Auer) writes:
> My problem was a tristate buffer with dual enable lines (SELECT
> and SELECT_BAR). In order for the gate to operate properly (and
> not burn up) the selects MUST be complementary (i.e., otherwise
> its output is unknown.) However, there is no way to stipulate
> this in a boolean equation for the library element. One
> "three_state" equation is "(!SELECT) & SELECT_BAR. Basically,
> the Synopsys engine thinks the gate is driving for a 00, 10, and
> 11. But, alas, the gate floats or burns up on two of these three
> conditions. Describing the "three_state" equation as "!(SELECT &
> !SELECT_BAR)", Synopsys thinks its okay to use 00, 01, or 11 to
> tristate the gate. Once again, two out of three are harmful.
> In practice, Synopsys will tie SELECT to power (or tie SELECT_BAR
> to ground) and use the other input to control the driving/three_state
> function. Saves gates, what the hey! :-(
>
> I filed this as a bug (ahem, STAR), and it is considered an
> "enhancement request", i.e., it will be fixed if they can find
> a clever, albeit, easy solution. I haven't heard anything on
> it in many months.
very strange. in the library compiler (cmos) reference manual, version 2.2,
page 5-10, you can find the "pin_equal" and "pin_opposite" attributes, which
as described, should do what you want. i tried creating a tri-state buffer
as you describe and it compiles fine under the library compile. however,
a compile of a simple verilog design gives the following:
Information: Unable to map three-state cells. (OPT-125)
Information: Leaving generic three-state cells in design. (OPT-126)
so: this is definitely a bug and not an enhancement request. i'll leave
it to you (John Auer) to update Synopsys.
Cindy Eisner, CAD group,
Zoran Microelectronics LTD
(as always, fine to use my name and any other info)
|
|
