( Post 58 Item # 1 ) ---------------------------------------------------------
From: bygate@ncrcol.columbiasc.NCR.COM (Terry Bygate)
> 5) What kinds of code (other than the examples in the documentation) will
> result in Synopsys generating really ill-behaved logic. Gated-clocks,
> decoded flop outputs feed back to the set or reset inputs, delay dependent
> logic, etc.
I would think that most of the 'gotchas' in Verilog would follow suit in
VHDL. I am sure there are some problems unique to VHDL though.
Anyway, a gotcha which we have encountered (in Verilog, which I have not
seen discussed on ESNUG), involves the use of signals which do not always
have known values. Synopsys does not "understand" invalid/floating inputs
and it can create a hazard with what is normally considered synchronous
logic.
This can occur in a state machine, which has some inputs that are valid
only during specific states. The designer can take care to qualify the use
of the input signals by what state they are sampled. During optimization,
Synopsys may 'borrow' a term from another state decode bit, and use that
term as the select line of a mux (or its equivalent in discrete gates) whose
output is used in the decode of another bit. When the input signal goes
unknown, then it propagates through the mux, which propagates through the F/F,
etc.
Our work around was to hand instantiate logic to gate off the signals when
they are invalid, and perform a dont_touch on the 'gating' logic.
The actual problem was discovered in the midst of lots of code, at a very
unappropriate time, therefore it did not get that well documented by the
person. I have not had time to trace the problem down to specific code
and submit it to Synopsys. I called the hotline and tried to describe the
problem, and got the response, "Well, if you could send us an example of
what you saw..." Anyway, we just watch for it now.
( Post 58 Item # 2 ) --------------------------------------------------------
From: janaka@ee.Princeton.EDU (Janaka Withana)
We got synopsys at an educational discount (more reasonable price compared
to commercial rates). The professor I am working for thought it would be
useful to have it both for classes (hopefully we can get a library to support
Xillinx FPGA's for class projects) and also since we are developing our own
flavor of VHDL for behavioral synthesis based on a theoretical "Behavioral
FSM" model. (This happens before going through "normal" Synopsys-type
synthesis).
So far I have only been using the simulator part of Synopsys and have found
it to work flawlessly. I was not really a first-time user because we had
used Vantage for simulation before. The synthesis part (of Synopsys) has
not been touched yet since we are waiting for our software to work properly
so that its output could hopefully be synthesised.
( Post 58 Item # 3 ) --------------------------------------------------------
From: jpa@yosemite.inesc.pt (Jose Pedro Abreu)
Hi there,
I am trying to integrate Synopsys's Design Compiler into the Opus framework,
and I can't create a proper Synopsys symbol library (.slib) from my Cadence
symbol cellviews.
We are currently using Cadence v4.2 and Synopsys v2.2b.
We have the "Cadence to Synopsys Interface" but the Design_Compiler complains
that the Cadence suplied libraries (both .slib and .sdb) are from an older
version and can't use them. The same thing happens with the libraries
generated from my cadence symbol cellviews.
Any helpful hint will be deeply appreciated...
Thanks a lot
ZP
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