( Post 57 Item # 1 ) ----------------------------------------------------------------
[ From: bygate@ncrcol.columbiasc.NCR.COM (Terry Bygate) ]
Subject: problem optimizing of floating inputs Esnug mailing 52, item #1
I have been using Synopsys for just under a year, working with Verilog and
VHDL and am far from an expert. Having said that ...
> 1) How useful is the FSM Compiler if you are using VHDL (as opposed to
> state tables) as a front end. It appears that you have to go through
> the regular compile/optimize process first...
The main disadvantage with VHDL is that all states of a FSM have to given
(not bad, I believe Verilog has a similar restriction), but VHDL does not
allow for wild cards/dont_cares. As an example, if you have a 3 decode bits,
and anytime bit 2 is set, you want the FSM to go to a particular state. You
can use a casex in verilog:
casex( present_state )
3'b1xx :
begin
...
next_state = 7'b101;
...
end
3'b011 : ...
In VHDL, I believe one would have to list all cases where bit 2 is set
(the syntax on the following may not be totally correct):
case present_state is
when "100" | "101" | "110" | "111" =>
...
next_state = "101";
...
when "011" =>
...
If someone is aware of a better way, I would love to hear about it. The
above example is not too painful, but if you have lots of decode bits, it
could get quite painful.
( Post 57 Item # 2 ) ----------------------------------------------------------------
[ From a Califonia Engineer ]
> I have been frustrated at times...maybe most of the time...with their tools
> and the hidden trap doors and gotcha's. Just this morning, I am wondering
> how on earth the calculate setup times. I will email their hotline, ask the
> question. Probably hear in a day or 2. (that isnt too bad i guess.)
>
> We should have hired one of their consultants while we were learning,
> but they want to much $$$.
>
> On the setup time, it tells me that the worst d input had an arrival time
> of 7.31 ns, but that it met constraints. Yet the max_period constraint was
> 6 ns. I dont get it. Does that sound fishy to you?
[ Reply from jcooley@sequoia.com (John Cooley) ]
I had similar doubts when I first used the tool until I looked at a timing
report and realized is was the Design_Compiler taking the latency of the
clock tree into account. (Which is what I'd want it to do!)
- John
****************************************
Report : timing
-path full
-delay max
Design : garbage_design
Version: v2.2b
Date : Mon Aug 10 11:02:49 1992
****************************************
Max Delay
Point Type Fanout Path Incr
--------------------------------------------------------
CLOCK_IN in 8 8.56 f 8.56
U45/Z BUFF 6 12.35 f 3.79
U34/Z MUX2 1 14.69 r 2.34
U56/ZN INV 1 16.45 r 1.76
U57/Z NOR3 1 18.56 f 2.11
garbage_3/D SFF 1 18.56 f 0.00
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