( Post 53 Item # 1 ) ---------------------------------------------------
From: Trevor <lupine!trevor@uunet.UU.NET>
Reply to Post 52 Item #1:
I have been using VHDL with Synopsys for some months
and have the following input ...
1) The FSM compiler is good for squeezing the last ounce
of speed or area from the synthesis tool. It seems to
produce good state assignments but its rather involved
to get it all to work right. The golden rule I learned
the hard way is to isolate the state machine from the
rest of the design (The "group -fsm" didn't work very
well when I tried it) and pass only the inputs and
outputs needed to the state machine module (ie: Do not
pass inputs which may not get used as the tool will
try crunching on them anyhow.
I had a design where I brought a complex record with
500 signals into the state machine but only 20 or so
were actually used. The state machine compiler tried
to compile a state machine with more than 500
inputs. Since the input PLA has 2 ^ 500 combinations
it had not finished after 10 days. I learned all this
from a Synopsys FAE who had just come here from Europe
and had seem similar things over there. He told me
(unofficially, of course) that the fsm compiler on
a computer like a 40MHz SPARC is good for around
30 inputs, 30 states and 30 outputs. I believe it is
wise not to push it.
The step you refer to is currently a work around for
some problem with the tool. It is currently required
to get the design mapped to gates before running the
state machine compiler.
2) The obvious answer is, of course, yes there are subtle
points to writing these descriptions ...
but isn't there always with these kind of tools? :-)
3) I use mvl logic for all my design and I defined a subtype
mvl of mvl7. This means all that has to be done to change
to a different logic type is to change the subtype
definitions.
4) If you are hoping to make the synthesis completely
transparent to the models, I think you are expecting
too much at this stage of the tools' development. You
will need to constantly consider what the synthsis tool
is going to produce from your code. You will need a
liberal sprinkling of conditional compilation statements
because the synthesis is a subset of the standard and
some VHDL statements don't make sense to synthesis. It
seems to me that I design to the synthesis tool, not
to the simulator.
5) The one that caught me was putting an assert statement
in the others => of a case statement by itself. The
synthesis tool does not support assert statements so it
ignored it and that meant there was nothing in that part
of the case statement. To correct, the tool built a weird
sort of latch which took a while to find. The only
indication was that there were timing loops when it
optimized.
There are of course numerous other funnies.
-- Trevor
Trevor Pearman
Network Computing Devices trevor@ncd.com
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