( Post 52 Item # 1 ) ----------------------------------------------------------------
From: mccrohan@e5sb.osdhw.syr.ge.com (mccrohan d. 7647)
We are just beginning a new program and will be making use of VHDL and
synthesis in a big way for the first time. All of our previous experience
is with Verilog. It appears that most current Synopsys user's are using
Verilog HDL as a front end, instead of VHDL. We would be happy to hear
from other people using VHDL as a front-end. At this point, we have some
rather basic questions that we are looking for answers to, like:
1) How useful is the FSM Compiler if you are using VHDL (as opposed to
state tables) as a front end. It appears that you have to go through
the regular compile/optimize process first...
2) There appears to be a lot of subtle points to writing state machine
descriptions in VHDL, particularly if you are after a really well-behaved
design (i.e., all unused states transition back to the reset state, or you
want Johnson counters instead of the normal, glitchy variety.
3) We are using the IEEE MVL9 system instead of bit, or Synopsys's MVL7.
Unfortunately, all of Synopsys's documents use bit.
4) As our models will be used in higher-level simulations (i.e., board
and sub-system) we want fidelity, in addition to synthesizability. In other
words, the models must intelligently propagate unknowns...
5) What kinds of code (other than the examples in the documentation) will
result in Synopsys generating really ill-behaved logic. Gated-clocks,
decoded flop outputs feed back to the set or reset inputs, delay dependent
logic, etc.
We would appreciate any knowledge anyone has...
-dm
( Post 52 Item # 2 ) ----------------------------------------------------------------
From: Jay McDougal <jaym@hpcvcbu.cv.hp.com>
Hello,
I came across the following bug while trying to ungroup a hierarchical
design that had children of children with dont_touch attributes.
I was using ungroup -all -flat to remove the hierarchy but there were
some cells in the hierarchy that I had compiled with dont_touches
because I wanted them to use special Flip-Flops. When the design
was flattened, the dont_touched modules were also flattened!!
To get around this problem I had to call ungroup -all repeatedly
until all the hierarchy was flat. This left the dont_touched modules
intact!
This was particularly disturbing because there were no warning/error
messages and I could have easily missed the fact that the modules
had been ungrouped and re-mapped to use Flops that I did not want
it to use.
Jay McDougal
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