( Post 47 ITEM # 1 ) -------------------------------------------------------------
[ From: mills@hwcae.az.honeywell.com (Don Mills) ]
Subject: Schematics (Synopsys version 2.2b)
I have come across three problems to date between the schematics
synopsys gives us and what most ASIC supplies will allow.
1. Some ASIC suppliers do not care for or allow feed-throughs
or netconnects to be used the design.
2. Often, a design is reduced and the need for some of the inputs
are removed as well, but the input remains on the symbol giving
you an unused input.
3. PWR/GND driving outputs of a level of hierarchy.
I have found a solution for items 1 and 2 above.
a. go into the level that has a problem
b. group -logic -design_name <new_name>
c. go up one level
d. set_layer cell_name_layer visible TRUE
e. ungroup <cell_name>
This should eliminate both the feed-throughs and the unused inputs.
Note that (b) above will only group combinational logic. If you
have FLIP FLOP's that you want to group with the logic, use:
group find( cell, "*" ) -design <new_name>
Does anyone have a solution for the PWR/GND problem?
( Post 47 ITEM # 2 ) -------------------------------------------------------------
[ From a Synopsys User In Texas ]
Subject: re: Post 42 Item 2 State Machines & PLA
It would be best to leave off my login and company name... I will catch
less flac from them...
I am responding to posting #46, Item #2, which talks about PLA
& State-machines... have been doing synopsys state-machines for 2 yrs now..
1) We use verilog and by using the //synopsys enum and
//synopsys state_vector in the verilog code I can use a group -fsm
2) This groups only the logic and flip-flops that are appropriate for
the state-machine.
3) compile -map_effor low, no structure, no flattening.
(This gets the logic mapped, so that when you do the group synopsys
knows which logic is connected to the state-machine.)
4) I then current_design down into this new group:
a) extract -minimize
b) set_fsm_encoding { }
c) reduce_fsm
d) set_flatten true -effort high -minimize single_output -phase false
(The preceeding statement is optional and works to produce
a state-machine that is:
flatter
Faster timinging
Larger gatecound
Larger fanin - if you technology does not drive
medium amounts of load then you don't what
to do this.)
e) compile -map_effort low
5) current_design to the original design
6) ungroup -flatten -all
(This allows the new state-machine logic to be combined and further
optimized with the rest of the logic in the module. )
Of course with anything in Synopsys, this is only one solution and I don't
use this for all my state-machines, as this is good for some, but not good
for others
There is no one solution for all problems...
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