( Post 46 ITEM # 1 ) -----------------------------------------------------------------
[ From: gbrooksh@comanche.ess.harris.com (Greg Brookshire) ]
Subject: VHDL synthetics
ESNUG,
Be careful using cla_inc_dec synthetics! I have seen three VHDL descriptions
which generated carry look ahead inc/dec synthetics with the up/down input
misconnected. I didn't discover the problem until I was doing gate level
simulations in RapidSim. Synopsys looked at my VHDL and the resulting
circuit and admitted they had a real bug. As a work around I brought out
count_plus_one and count_minus_one to my entity. This forced dc to use
a separate cla_inc and cla_dec. Synopsys' fix was to change our synthetic
library so that when dc looked up a cla_inc_dec it really got a circuit with
separate inc and dec in parallel. This allowed me to use my original VHDL,
but my work around ended up being a faster circuit.
Greg Brookshire
VALID VHDL -> Synopsys -> RapidSim & Quickturn & VLSI
( Post 46 ITEM # 2 ) -----------------------------------------------------------------
[ From: Trevor <lupine!trevor@uunet.UU.NET> ]
Subject: PLA & State Machines
I have been having a lot of problems with compiling state machines. I use VHDL
records that typically bring in unused inputs to the state machine. An FAE from
synopsys took a look at my code and said that the input PLA keeps all the unused
inputs around and so the number of input combinations is much bigger than I had
assumed. I had one design that ran for 8 days before I killed it. The FAE said
that it was trying to compile over 1100 inputs. The state machine part of the
design was only 19 states with some 20-30 inputs affecting the state machine.
The reason for this was given as some kind of philisophical argument about not
removing unused inputs in case they are used later.
I didn't really understand this argument but what it means is that state machine must only have inputs brought in which are actually relevent to the state
machine. This means, of course, that the state machine cannot be embedded in
a module but must be structured for the synthesis tool. (Can be horrible code).
Trevor Pearman trevor@ncd.com
Network Computing Devices
( Post 46 ITEM # 3 ) -----------------------------------------------------------------
[ From: jeffs@kpc.com (Jeff Smith) ]
Subject: Synopsys FSM
I have a design with a large Moore state machines (1000+ gates.)
I initially used FSM compiler it to try to reduce the area.
It had little impact so I tossed it. After initial top level timing
analysis we found that several of the inputs to the state machine was
badly delayed and that "normal" Synopsys could not compensate for it.
I widened the state vector and re-enabled the FSM compiler. It reduced the
delay by several nS (which was enough) and, once again, had little impact
on the gate count. I repeated this with a couple of smaller ones (600+
gates) and got similar results. It saved me days of dittling around with
a working design.
( Post 46 ITEM # 4 ) -----------------------------------------------------------------
[ From: cindy@ca45.zoran.hellnet.org (Cindy Eisner) ]
Subject: memory usage in v2.2b
has anyone seen an extreme increase in memory use between versions 2.2a
and 2.2b? i have a block which compiles using ~70M under v2.2a, and
fails with an "out of memory" message at ~250M under v2.2b.
it's fine to use my name and company name.
cindy.
Cindy Eisner
Zoran Microelectronics LTD
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