PLEASE NOTE: If you're having mail sent to "jcooley@sequoia.com" bounce
back to you, please try using "jcooley@sds.sequoia.com" !!!
(They've recently been "upgrading" the mailing software at
my site and still have one or two bugs to find and fix.)
( Post 45 ITEM # 1 ) ----------------------------------------------------------
[ From: prasad@asic.enet.dec.com ]
E-Mail Synopsys Users Group (ESNUG) sounds like a very good idea. Even
though Synopsys Hotline is usually very prompt and responsive, it would be
nice to hear from fellow Synopsys users about specific problems, workarounds
etc..
Our group (here at DEC) has been following HDL-based design methodology for
quite a few years now. I have been an HDL user (VHDL, Verilog, DEC internal)
and synthesis tool user (Synopsys, other external, and DEC internal tools)
for a long time; Synopsys user since their inception 1988....
( Post 45 ITEM # 2 ) ----------------------------------------------------------
[ "gotcha" submitted by a California user]
This is not really a bug but sort of a gotcha. We design using verilog
code and use Synopsys to convert to gates. Our feedback loop
is to take the gate level Synopsys output and run it in the verilog
code's test environment. If they run the same, everyone's happy.
We have designs with hierarchy and use ungroup to flatten it, to get each
instance name concatenated with the module instance name which is fine.
Where the gotcha is that internal nets are not treated the same way. Instead
they are uniquified. So where you had a logical name like "strobe_n" I found
"n2435" in it's place. What this meant is that we had to change all of the
net references in our test code to be in the form "register_instance_name/Q".
(Which took some time.)
( Post 45 ITEM # 3 ) ----------------------------------------------------------
> [ From: Niel Barrett <nbarret@synoptics.com> ] (Post 44, Item 3)
>
> Synopsys has a hard time dealing with long serial shift/parallel load
> registers, where individual bits of the parallel load register are fed
> from misc combinatorial logic blocks.
>
[ From: ronny@zycad.com (Ron Karpel) ]
I had similar experience trying to synthesis a 32x32 register file. I
had to kill the job after several days. The solution was similar to
Niel's. I created an hierarchy of registers (4 registers in each
module, and a top level module that instantiates 4 of the lower ones).
This compiles in about 15 minutes. It takes about 100 lines of VHDL to
describes the register file instead of just 2 or 3.
Ron Kerpel
[ From: Pierre-Yves Thoulon <pyt@desire.grenoble.hp.com> ]
Is this an HDL compiler bug or a Design compiler bug ? In other words,
has any body seen anything comparable using VHDL descriptions ?
Pierre-Yves Thoulon,
Hewlett-Packard France
Grenoble Networks Division.
( Post 45 ITEM # 4 ) ----------------------------------------------------------
As of: Thursday, June 18th
The ESNUG mailing list has an estimated readership of: 453
( Post 45 ITEM # 5 ) ----------------------------------------------------------
Call For Discussion! Call For Discussion! Call For Discussion!
Do you use the FSM Compiler ? What have been your experiences
with it ?
Does it typically reduce, increase or not change the gate count
in YOUR experience?
What bugs/gotchas/techniques have you found or developed in using
the FSM feature?
Send in your input and become known the world over!
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