( Post 44 Item # 1 ) -----------------------------------------------------------------
From: hoang@homer.super.org (Dzung T. Hoang)
Subject: Re: ESNUG: Post 41
Does the ALWAYS bug manifest itself when using VHDL?
( Post 44 Item # 2 ) -----------------------------------------------------------------
[ Another DAC attendee's impressions ]
The Cadence Synthesis tool does some form of timing analysis but will not
automatically insert logic to correct setup/hold violations - this is
a manual process - the timing analysis portion and Veritime do not
necessarily use the same algorithms!
( Post 44 Item # 3 ) -----------------------------------------------------------------
From: Neil Barrett <nbarrett@synoptics.com>
My first contribution, feel free to use my name, etc:
Synopsys HDL-Verilog compiler Ver:2.2a
Synopsys has a hard time dealing with long serial shift/parallel load
registers, where individual bits of the parallel load register are fed
from misc combinatorial logic blocks.
Where would you use such a "weird" block?
Lets say had a half a dozen 16 bit counters on a chip, whose contents you
wanted to examine. You could do a parallel load of the contents of all 6
counters into a 96 bit maintenance register and then do a serial shift
out of that register, thus using one pin to monitor all 96 bits. This is the
general idea. You could also use it to load config type information to a
chip.
But now extend this idea to the ability to monitor the output of any
block of combinatorial logic.
In my particular instance I had 192 bits that I was interested in. So I
instantiated in verilog
reg [191:0] maintReg;
This maps well, and is a syntactically and semantically legal in both Verilog
and Synopsys. BUT -- here is the key, it took more than 36 hours to synthesize
a design that had about 3000-4000 gates when I used one long 192 bit register.
(Sun SparcStation2 with 96MB)
I have called the Synopsys Hotline and they are aware of this problem and the
AE acknowledged that it is a BUG.
The fix/hack I found is: break up the 192 bit shift registers into chunks of
24 bits and call them separate modules. Then cascade the LSB of one to the
MSB of the next and make the chain out of the smaller pieces. Also, use the
"dont_touch" attribute on them when compiling the larger module.
Thus, I was able to take the same design and synthesize it in approximately
16 minutes. The total number of gates came out to be roughly the same, only
the difference in the CPU time.
Anyway, that was my experience.
neilB
Neil Barrett
SynOptics Communications Inc.
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