( Post 42 ITEM # 1 ) --------------------------------------------------
What follows are some reactions I've received from the the recent
mailings. -John
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Hi, I'm a PhD student in [an American university]. My research interests
include ATPG and Synthesis. We've just recieved and started using some
Synopsys products. Please add me to the e-mail group.
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The Synopsys users have needed something like this for a long time since
their support really #$%&%@*. What are the odds of getting YYYYY YYYYY
and the other characters at Synopsys involved with this thing ? Sign me up !
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PLease take me off this mailing list, I'm not sure how I got on it
in the first place.... I debugged enough Synopsys for one lifetime.
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Please add my name to the E-Mail Synopsys Users Group list. I can use
all the help I can get - Synopsys is driving me crazy!
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( Post 42 ITEM # 2 ) --------------------------------------------------
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
SYNOPSYS BUG ALERT SYNOPSYS BUG ALERT SYNOPSYS BUG ALERT
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
I just recieved a bug report from my chip vendor with a warning about Synopsys
having problems with it's Verilog netlister.
Apparently, if you have a hierarchical design with nets connecting to multiple
submodules, the netlister is outputing ASSIGN statements for these nets.
What this means is that after you compile and write out your gate level designs
(in Verilog) that the design will pass Verilog simulations without error but
that you'll have errors when you try to tape out for final release of your chip.
Synopsys does know of this problem and they'll fix it with their usual
efficiency.
WORKAROUND UNTIL THEN:
1) When done with all compiling, flatten your design by giving a
"ungroup -all -flatten".
2) Write your design out in Verilog format via a "write -format verilog
-output design_name"
3) Hand edit each "assign foo = bar;" to be a buffer from your technology
library that connects "foo" to "bar". Also, be doubly sure which
signal is the driver and which signal is driven. (WARNING: If you just
eliminate "foo" and replace it with "bar", be sure that you're not
violating the fanout limit of "bar"!)
If I find a little time, I'll be writing a tool that will do step 3. If
anyone wants it, they'll be welcome to it.
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