Here's two different solutions for the ALWAYS bug that have come up.
( Post 41 Item # 1 ) --------------------------------------------------
From: rawlins@titan.eng.hou.compaq.com (Paul Rawlins)
Subject: ESNUG: Post 40, Item 1
Try this:
input [42:0] fooby; /* vector definition */
wire [23:17] sub_fooby = fooby[23:17];
always @( sub_fooby ) /* using a subfield of vector */
It should work for both simulation and synthesis.
( Post 41 Item # 2 ) --------------------------------------------------
From: jcooley@sequoia.com (John Cooley)
Subject: ESNUG: Post 40, Item 1
What follows is a NAWK script that fixes the ALWAYS bug that I've
used for a few designs.
#
# ALWAYS - a tool that searches Verilog code for "always @(fooby[23:17])"
# and replaces it with "always @( fooby )" in accordance with
# fixing Verilog code for the Synopsys ALWAYS bug.
#
# To invoke: SUN_PROMPT> nawk -f ALWAYS input_file > output_file
#
# Please note: the input_file can not be the same as the output_file!
#
BEGIN {
print " \n \/\/ This file has been checked for the Synopsys ALWAYS BUG \n"
inalways = 0
}
{
if ( ($1 == "always" && (0 != index($0, "@"))) || inalways == 1 )
{
inalways = 1
gsub(/\[[0-9]+\:[0-9]+\]/, "")
gsub(/\[[0-9]+\]/, "")
if ( 0 != index($0, "\)"))
inalways = 0
print $0
}
else
{
print $0
}
}
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