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SYNOPSYS BUG ALERT SYNOPSYS BUG ALERT SYNOPSYS BUG ALERT
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The Synopsys Verilog reader has difficulty handling "complex event-expressions"
within ALWAYS blocks.
To give an example:
input [42:0] fooby; /* vector definition */
always @( fooby[23:17] ) /* using a subfield of vector */
.
.
.
Causes Synopsys release 2.2a and release 2.2a-6762 to be rather upset and
unhappy.
Whereas, if the above was changed to:
always @( fooby ) /* using whole vector */
.
.
.
All would be fine because this would be considered a "simple event-expression".
WORKAROUND:
Even though you may be using only a subfield within a vector, it's best to
present the whole vector as the event-expression within ALWAYS blocks.
Synopsys will very readily optimize out any unused subfields, so it won't
effect the gate level model in an adverse mannor and the design can be
worked on within Synopsys.
How this will impact on systems level simulations is another issue altogether.
Because the change in anything that's found within an event-expression causes
everything in the ALWAYS loop to be re-evaluated, giving the whole vector may
cause the Verilog behavioral simulations to run slower.
- John Cooley
ASIC Designer & CAE Grunt
Sequoia Systems, Inc.
Marlboro, Massachusetts, USA
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