( SNUG 02 Item 19 ) -------------------------------------------- [ 5/15/02 ]
Subject: The Synopsys 2002 Report Card
There's been a noticable crop of killed off smaller technologies at Synopsys
this year. ECO Compiler's has been End-Of-Lifed as Behavioral Compiler is
rumored to be. Eagle-i is dead. The Synopsys 0-in rivals 'Ketchum' and
'Verification Analyst' have been killed even before they were announced.
Nobody's seen Protocol Compiler for the past 12 months.
Then there's are the niches Synopsys is messing up in. Chip Architect and
its secretive Hidden Dragon replacement both suck. Everybody *still* hates
designing chips in C/C++ and now that hatred is being focused on SystemC.
Synplicity's kicking their ass in FPGAs. Last year, Synopsys owned 35% of
the FPGA synthesis market. Now they only own 14%! (Ouch.) Users yawn at
their day-late-and-a-dollar-short Scirocco VHDL simulator. And new this
year Mentor's FastScan appears to be seriously threatening TetraMAX in the
ATPG market. Oops.
There have been two noticable improvements this year, though. Formality is
still losing to Verplex, but it's been making a very noticable comeback in
the eyes of customers. BSD Compiler's no longer hated by users. It's moved
up to being just distrusted.
Other than FPGAs, most of these wounded/dying Synopsys tools are playing in
under $10 million markets. That is, they're mostly expendable experiments.
If they succeed, great. If they fail, kill'm. Let the market decide. The
only baby tool they can't ignore, though, is Hidden Dragon. In terms of
future tools, Hidden Dragon (or something like it) must work.
On the other hand, Synopsys has made and still makes a boatload of money off
of many key EDA tools. Design Compiler owns 87% of the $178.6 million RTL
synthesis market. PrimeTime owns 97% of the $26.6 Static Timing Analysis
market and it's successfully expanding into SI. Synopsys VCS goes roughly
50-50 with Cadence NC-Verilog in the $108.6 million compiled Verilog market.
DesignWare pulls in $45 million capitalizing the small IP market. DFT tools
pull in $39.9 million with a 51% market share. Formality has 44% market
share and pulls in $14 million. Vera has 43% and does $12 million. Power
Compiler owns its little niche. Module Compiler owns datapath.
But the two most important pieces of EDA news this year are that Synopsys
clearly dominates the physical synthesis market:
Synopsys PhysOpt ######################################## 600 tape-outs
Magma ####### 100
Cadence PKS ## 36
Monterey 3
and that Synopsys is acquiring Avanti.
"I think it's also especially bad news for Cadence. While their
corporate officers may simply shrug this off, I believe this merger
hits them where it hurts the most. They've been struggling to get
PKS production worthy, trying to add synthesis to their place and
route tools. But their toolsets and framework were always kind of
ad hoc (some would say baling wire and spit) and they've had
predictable results. Meanwhile, Synopsys looked from their position
of strength (synthesis) and forged a new approach based on their
strength and an astute analysis of the most basic problem in the
backend flow. The result is PhysOpt, and it is off to such a good
start that even many small firms are beginning to shell out the
4X DC price to start working with it. Now that Synopsys will add
what many consider to be best-in-class place and route to their
toolset, Cadence must feel great pressure."
- Mark Wroblewski of Cirrus Logic (in ESNUG 384 #8)
"Why is Aart smiling? Let's look at the numbers. Fifteen thousand
DC current users transitioning to PhysOpt in two to three years at
an average selling price of $180,000 would mean a total market of
nearly $2.7 billion dollars even without market expansion. You can
play other more conservative scenarios and still come up with
numbers that will make Aart smile."
- Kevin Walsh, VP of Sapphire Design Automation, 12/15/00
[ Editor's Note: Please feel free to email me at jcooley@TheWorld.com if you
you have gripes/praise/questions about any part of this report. - John ]
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\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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