( SNUG 02 Item 5 ) --------------------------------------------- [ 5/15/02 ]
Subject: NC-Verilog & NC-SIM, VCS & Scirroco, ModelSim, Fintronics
GONE COMMODITY: From the Dataquest 2000 market share numbers and reader
response, Synopsys VCS and Cadence NC-Verilog each own about half of their
market. ModelTech owns 73% of the mixed Verilog/VHDL simulation market
and nobody really cares about pure VHDL simulators like Scirroco any more.
Dataquest FY 2000 Simulator Markets (in $ Millions)
Verilog Total ######################################## $120.7
Synopsys ################## $55.5 (46%)
Cadence ################## $53.1 (44%)
Fintronics ## $7.2 (6%)
others ## $4.8 (4%)
Verilog/VHDL
Mixed Sim Total ############################ $85.2
ModelTech ##################### $62.2 (73%)
Cadence ####### $21.3 (25%)
others # $1.7 (2%)
VHDL Total ####### $22.1
Cadence #### $10.8 (49%)
Aldec ## $6.6 (30%)
Synopsys # $4.0 (18%)
others $0.7 (3%)
The other thing to notice in this data is that 52.9% of designers do pure
Verilog design, while only 9.6% do pure VHDL. The remaining 37.4% have
their feet in both Verilog/VHDL worlds probably because of 3rd party IP.
"Fintronics was the surprise this year. They found out that the LINUX
server farm market is a gold mine that everyone else is missing."
- Gary Smith of Dataquest
"Don't use Verilog. Wish I did."
- Brent Lawson of Texas Instruments
"I never used NC-Verilog. I'm happy with VCS. VHDL is a four-letter
word. (Count them if you don't believe me :-)"
- Oren Rubinstein of Nvidia
"VCS and NC-Verilog are like Coke and Pepsi."
- Dave Chapman of Gold Mountain
"We use VCS. It was faster in our last tests plus we're still waiting
for further integration of Vera into VCS.
- Tom Heynemann of Compaq
"I strictly use ModelSim for both VHDL and Verilog simulations. Happy
with it."
- Kevin Hubbard of Siemens
"For small quick sims, I use ModelSim. For full tests, I use
NC-Verilog. ModelSim is useful for sub-module debugging on my
PC. NC-Verilog is useful for the Unix (X-Windows) platform with
files located on various servers. This just happens to be my setup,
and it works well. No interest for now in the Synopsys Scirocco VHDL
simulator, I'm writing everything in Verilog."
- Eric Mitchell of Cypress Semiconductor
"We needed to revert back to NC-Verilog. Until now we've used VCS for
everything, but next generation we may be migrating back to the
old guard."
- an anon engineer
"We use Modeltech for most of our internal simulations. The majority of
my consulting customers use Synopsys VCS."
- Tom Moxon of Moxon Design
"We would like to see a more direct and easy path for co-simulation of
SystemC into the MTI flow. Their new 5.6 version includes a C-debugger
so I assume they are moving down that path although not as fast as we
would like."
- an anon engineer
"VCS. For legacy reasons."
- Kalyan Chakravadhanula of Texas Instruments
"We have access to MTI, VCS and NC-Verilog. Personally I prefer
NC-Verilog. While I have not benchmarked them, VCS and NC-Verilog
are about the same speed for RTL simulations. NC appears to compile
faster. Once you use the PLI, VCS slows way down. Systemsim
(Superlog) is about the same speed but their compile feels slower,
again no benchmarks. Modelsim is nice for GUI users, but always
just feels awkward to me there is no "xl mode" with a singl
invocation like XL, NC, and Systemsim. VCS is only two easy steps,
but MTI is too many steps."
- James Lee of Intrinsix
"We deal with a mix of Verilog/VHDL, and for us Cadence NC-Sim running
on HP is our tool of choice for front-end sim. The environment's
clunky and goes down in flames every so often, but I suspect this to
be more related to HW/SW/network issues. (Hey, if I had my druthers,
I'd rather have an UltraSparc on my desk.) Compared to previous
Cadence Leapfrog versions, it seems fairly stable. There are a few
PC-based renegades here who swear by ModelSim, but I just don't feel
the necessary horsepower is there. No way would we bring VCS into
the picture."
- an anon engineer
"Last eval was 4 years ago. VCS won the speed war at that time but I
am not up to date."
- Scott Vincelette of Flarion
"I was earlier working in TI doing ASIC library (simulation models
and VITAL) development. My impression was that ModelSim is the best.
NC-VHDL is close to it. We used VSS years ago, but it was very slow
and our customers mainly used to ask for ModelSim or Leapfrog/NC-VHDL."
- an anon engineer
"Being a mostly Cadence house, we are using NC-Verilog. We do want to
evaluate and benchmark VCS, however. We would use NC-SIM if NC-Verilog
is chosen over VCS. ModelSim would be nice but since we already have
licenses for VCS and NC-Verilog, we aren't gonna spend money for
another tool. Scirocco would be interesting if we used VHDL (which
we do not)."
- an anon engineer
"Synopsys has put a lot of effort into VCS recently, especially adding
(finally) the Verilog-2000 "synthesizable subset". I have yet to
use those constructs, though, so I can't vouch for the quality.
I *did* have a significant case where VCS 5.2 in 2state mode simluates
*faster* than VCS 6.0.1/6.1 in the same 2state mode. In fact
5.2/2state was faster than *any* VCS 6.1 combination of optimization
switches. I'm working with Synopsys ACs on that. Don't know how
much that might affect other people."
- Kris Monsen of Mobilygen Corp.
"I'm a VHDL guy, not a Verilog one, thus I have little interest is some
of the above mentioned Verilog tools. However, my current FPGA/ASIC
flows are designed around ModleSim. Synopsys has never had a competent
offering in the VHDL simulation game. Hopefully the Scirocco compiler
will fix some of their deficiencies.
I actually write VHDL code which is "dumbed down" so that Synopsys VSS
will compile it. None of the other VHDL simulators (or synthesis
tools) takes such a small subset of VHDL. It will be interesting to
see how fast they come up to speed with Verilog-2000 (which adds many
of the features from VHDL into the Verilog language)."
- David Bishop of Kodak
"Cadence all the way! Synopsys tools don't follow the IEEE standard
as closely, and therefore has some delays that happen incorrectly.
Speedwise Cadence seems to win out, too."
- Fraya Cohen of Procket Networks
"Some years ago, I used QuickHDL and ModelSim to do mixed simulations
(VHDL/Verilog) with 100K gates design. It was working fine.
Today, I am using NCSIM simulator, and it's a pain. This tool does not
know how to handle mixed simulations, Signalscan makes NC-SIM crash,
each new version has its bug. NC-Verilog works fine but if you want
to do VHDL-Verilog simulations, use ModelSim."
- an anon engineer
"I prefer VCS over NC-Verilog. A lot of my simulations are gate level
and some require SDF backannotation. VCS having the ability to compile
SDF reduces my memory usage and runtime. It is also more mature at
the gate level. One problem that has crept up occasionally with VCS
is mismatches on no timing scan chain simulations because of event
scheduling. I believe Synopsys has fixed this."
- an anon engineer
"We only use NC-SIM and ModelSim, so I can not comment on VCS part.
Between ModelSim and NC-SIM, personally I prefer ModelSim a bit more.
We have no problem for NC-SIM and ModelSim to integrate into our
design flow.
We are interested to Scirocco VHDL simulator as well because of it's
SystemC simulation support."
- Hui Fu of Infineon
"We had Verilog-XLs, NC-Verilogs and VCS - everything. It was always
a neck-to-neck between NC-Verilog and VCS although recently we have
observed that VCS has surged ahead with release 6.1. NC-Sim would be
interesting to try and we are looking at it moreso because we have
frightful prospect of sharing IP from two different languages for
future products. We will also look at VCS+Scirocco combination
for mixed mode simulation. It is the most expensive combination of
all. Interestingly, Synopsys is now pushing for Linux platforms,
especially for VCS because they have seen very good benchmarks on
superfast Intel CPUs."
- an anon engineer
"We use NC-sim. We have not benchmarked VCS so I cannot compare.
NC-Sim is very reliable and fast with only a few problems in
backannotated netlist simulation."
- Karl Kaiser of Resonext
"We're using VCS and are very happy with it. Dropping Covermeter in
for free was a good idea."
- Jeff Waite of Netergy Microelectronics
"We normally utilize ModelSim to suppport mostly VHDL designs. We have
not considered Scirocco and don't expect to unless ModelSim seriously
tanks in performance."
- Scott Campbell of Motorola
"We benchmarked ModelSim vs. NC-Sim (with NC-VHDL) independently without
any support from the vendors. NC-Sim is clearly the winner when it
comes to simulation speed. However when it comes to interactivity, i.e
the ability to change your RTL and launch another simulation, we found
ModelSim a little bit easier to use (lower turnaround time). NC-Sim
has a command to "re-invoke" the simulator after you change the RTL,
but it goes through an elaborate phase which is sometimes time
consuming. The NC-Sim GUI and waveform viewer have improved a lot in
version LDV3.4. Our benchmarking was done with versions LDV3.2, LDV3.3
and Modelsim 5.5 PE. Overall, I would say that I would pick NC-Sim
over the ModelSim. I have heard good reviews about VCS, but never
tried it. We noticed a big improvement in memory usage going from
LDV3.2 to LDV3.3."
- an anon engineer
"Where I work, we are fairly happy with Cadence NC-Verilog. We use
mixed Verilog with IP in VHDL, so we would like a lot better mixed
language support in all of the EDA tools."
- Mark Gonzales of IBM
"We use VCS based on the impression that it ran faster, but also because
we wanted to use a short list of vendors. We're using other Synopsys
tools."
- Curt Beckmann of Rhapsody Networks
"I noted that in one tract at HDLcon'02 all the papers but one said
basically, 'we are working with (standards groups, users, our
competitors) to come up with the best solution'. This was evident
in the PLI discussion from Lee Tatischef of Cadence (Best paper),
the System Verilog Accellera standard presentation, and the
Assertion standard presentation.
The last paper in the group was from a Synopsys employee on the
Direct-C interface he was working on. He made no mention of
cooperation/standards. It would be nice if he/Synopsys worked
with the other vendors. It would appear that Co-Design's Systemsim
simulator has what they call 'C-blend', which is a similar concept
to Synopsys's Direct-C. It would be nice if these guys worked
together like Cadence did with Synopsys and MTI. I'd hate to see
more needless divergence in the tools."
- James Lee of Intrinsix
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