( SNUG 01 Item 23 ) -------------------------------------------- [ 3/28/01 ]
Subject: O-In, Synopsys NDA "Ketchum", & NDA "Verification Analyst"
THREE LITTLE PIGGIES: In my DAC'00 Trip Report, I wrote about O-in and a
Synopsys tool that was shown only under NDA to customers:
"Under NDA Synopsys discussed two related but different tools. The
first one was a tool very much like 0-in called "Verification
Analyst" (VA). What VA does is it has "Temporal Assertions" very
much like 0-in's "Checkers" and an "Observation Based Coverage
Engine" (also like 0-in.) And, just like 0-in, you feed it your
design, your test suite, and your Assertions, and then you play the
20-Question Game to see what situations aren't covered by your test
suite, etc. Verification Analyst was the result of an off-site
brainstorming session with the Synopsys VERA, Covermeter, and VCS
R&D guys. VA's main difference from 0-in is that its Assertion
language is supposedly simpler and more power to use over 0-in;
it can easily traverse hierarchies and handles multiple clock domains
without a problem (or that's at least what Synopsys claims.) Their
other bragging point is that VA will run super fast because it'll
have direct links to the VCS simulator through the Synopsys VeriC/DKI
interface that they discussed under NDA in their demo suite. (Other
tools will have to go through the slower PLI.)"
- from the 2000 DAC Trip Report ( DAC'00 #16 )
What's transpired since then is that "Observation Based Coverage Engine"
(OBC) has become productized into a preliminary next generation code
coverage tool. There was even a customer paper in this year's SNUG'01
proceedings about this tool! (Take a look at "An Improved Code Coverage"
by Jeff Deutch of Avici -- that mysterious 'Z' code coverage tool he's
talking about is Verification Analyst's OBC!)
There was another Synopsys NDA verification tool I outed in that same
DAC'00 report:
"The second Synopsys NDA demo during DAC covered a product called
'Ketchum' (which was named after the Pokemon character 'Ketchum'
who tries to catch all other Pokemons.) Ketchum is a semi-formal
automatic test generator that creates functional (not ATPG) vectors.
It typically focuses on FSMs and can craft a small set of functional
vectors that will test every state in your chips internal state
machines."
The new gossip on Ketchum is that Moto (Austin) and possibliy ST Micro
(Agrate, Italy) are doing the 1st round of alpha testing. I'm told that
the way Ketchum works is Ketchum thinks for about 12 hours on your design
and then spits out a Verilog stimulus file. That Verilog file runs for
2 minutes in your chip's test suite and, voila!, you have 100% functional
coverage (or not.) The actual Ketchum runtimes range from minutes to
infinity. It's *very* alpha. Ketchum uses a Synopsys proprietary assertion
language that's made to work with VCS, Scirroco, Vera, and CoverMeter.
(This assertion language may be opened by Synopsys later.) Synopsys tells
the Ketchum customers that the DW team is using Ketchum for its internal DW
development, but I don't know if that true or not.
On the not-so-secret front, O-in also played prominently at both SNUG'01
and the HDL Con'01 conferences:
"0-In Check/Search (0-In Design Automation - http://www.0-In.com)
* Use 0-In pragmas to embedded checkers in RTL or in separate
file.
* Same (//0-in) checkers used in simulation (0-In Check) and
semi-formal (0-In Search).
* O-In Search is an execution path amplification tool. Provide
seed stimulus and tool will systematically try and find way
to fire checkers by changing the stimulus applied to the design.
* Latches not currently supported - planned Beta @ DAC JUN/01
Now if Verplex and 0-In would get together and settle on a common
pragma that would be an awesome solution. Write a set of assertions
to use with simulation, semi-formal and formal.
- Jerry Vauk of Sun MicroSystems
"Foster's 'Assertions Targeting a Diverse Set of Verification Tools'
won the HDL Con'01 best paper award.
Assertions inserted in the HDL were very powerful and are used in
many verification tools. Harry showed a method that allows the same
assertions in your HDL to be used by many different Verification
Tools: 0-in, BlackTie and others.
More information can be found at http://www.verificationlib.org "
- Dan Joyce of Compaq
"Assertions Targeting a Diverse Set of Verification Tools"
by Harry Foster (HP, foster@rsn.hp.com)
----------------------------------------------------------
* Use OVL assertion monitor library to facilitate using the
same assertions in simulation (0-In Check), semi-formal
(0-In Search) and formal (Verplex BlackTie).
* Modules in assertion library (Open Verification Library - OVL)
were modified to encapsulate the related set of 0-In assertion
directives.
* Pushing Verplex and 0-In to remove this redundancy - one set
of assertions for simulation, semi-formal and formal!
It was the best paper I attended at HDL Con'01."
- Jerry Vauk of Sun MicroSystems
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