( SNUG 01 Item 18 ) -------------------------------------------- [ 3/28/01 ]
Subject: TetraMax, Mentor's "FastScan", Synopsys "BSD Compiler"
A MISS AND A HIT: It's unanimous -- everyone who has worked hands on with
Synopsys' BSD Compiler absolutely detests it. BSD Compiler is reliving the
life of its older brother, Test Compiler, when ESNUG was swamped for almost
2 years with "I hate Test Compiler" customer letters. Now, years laters,
Test Compiler was eventually debugged and became passable -- only to be
replaced by Synopsys TetraMax. For a while Mentor's FastScan tools had a
quiet reputation amoungst those-in-the-know as being the best in class.
TetraMax has jumped into their place within the past 18 months. (The '99
DataQuest numbers give Synopsys 52.2% vs. Mentor 24.0% marketshare. "I
see Physical Compiler driving the dominance of Synopsys in the DFT market,"
said Gary Smith of DataQuest. "and Mentor's marketshare should continue
to shrink.")
"If you are referring to BSD Compiler by Synopsys, our opinion is that
it is terrible. We have told Synopsys this before. In my opinion, it
seems to be a tool that was written by some co-op student given its
completeness. In Synopsys defense, they have shown a good bit of
interest lately in improving the tool (since I told them my true
opinion). However, the tool is so far out from being useful that we
have denied being involved in developing it further. I usually help
out if the tool is at least somewhat close to being useful but in this
case it's not even practical. This tool failed even to write the BSDL
(ie: extract the JTAG and write BSDL) for a test case that Design
Compiler itself generated the JTAG for. That is, we used Design
Compiler and the DesignWare JTAG cells to generate a simple test case
and then tried to extract the jtag and write bsdl using the bsd tool.
It failed even on this."
- Russell Petersen of Scientific Atlanta
"As for Synopsys BSD Compiler, it should be flushed down the toilet!"
- Michael Hede of Conexant
"We use TetraMAX, and have had no big problems so far. Some friends
swear by FastScan, but I don't have direct experience.
We tried an earlier version of BSD Compiler, in January through March
2000, and gave up. We now use Logicvision's JTAG insertion tool. We
like it OK, the advantage is it inserts at RTL level, as opposed to
Synopsys gate level. That allows us to easily simulate, and use formal
equivelence checking. I would not consider BSD Compiler again."
- Paul Schnizlein of Agere Systems
"We used to use Sunrise and then wanted to use TetraMax; however, the
first release of TetraMax was purely for marketing and it couldn't
support the complicated designs that we have. As a result we now use
FastScan and DFT Advisor from Mentor only because that's what we are
fluent with. Our DFT guy really likes them and hasn't ever run into
any significant problems. Note that we do use DCXP to do scan
insertion, but not for stitching."
- an anon engineer
"I prefer Fastscan (or the internal tools from Philips) over anything
Synopsys offers for vector generation. Both sets of tools give more
compact vectors and thus shorter test times than TMax. However I still
believe that if using DC for synth, then using "-scan" on the compile
and stitching the chains using DC/TC is the best approach."
- Chris Byham of Philips Semiconductors
"Fastscan is still the leader in technology since it can handle all
fault models - stuck-at, transition, path delay, and IDDQ. However,
TetraMax is fast catching up, perhaps by year end. TetraMax's
debugging tool beats DFTinsight hands down.
DCXP is only for older or legacy designs. No one should touch it
anymore. Don't know why anyone would bother with something like
BSD Compiler or BSDArchitech (Mentor). It's just a couple hundred
lines of code and once written, can be modified and re-used on many
projects."
- an anon engineer
"We're using TetraMax here. It seems to work. It's very picky about
library models - the parser found holes in the UDP tables for several
of our library cells that no other tool complained about. Probably
this is a good thing, although it took us a while to fully understand
the problem.
Hint to library vendors: Try compiling your library for TetraMax. You
might learn something interesting. :-)
Hint to Synopsys: A little more information for those sorts of library
problems would be nice. Also, how about making the library-parsing
part of TetraMax available freely to all library vendors? End-users
shouldn't have to debug this stuff for them."
- Howard Landman of Vitesse Semiconductor
"I have used both FastScan, 3 years ago and TetraMAX last year. The
TetraMax folks have done a lot to make this tool fast and usable. I
like the control and feedback I get from this tool. From what I have
read, no first hand experience, FastScan has not kept pace. Right now
because of my experience and my client base I would prefer TMAX."
- Tom Tessier, t2design
"LastDay!: DFT, Scan, & Test oh my!
I'm the only one who cares about this at the moment, but...
Synopsys added Test Design Rule Checking to the RTL level, so you don't
need to get all the way through your chip level synth to find out that
your test methodology doesn't work. I found doing test for the [ chip
name ] that it was by far easier to go all the way back to RTL to make
something the tool wants than to try to convince it that all was okay.
This tool should make life much easier.
TetraMax now incorporates the "Full-Sequential" scan ATPG algorithms
from the Sunrise product. (That means not all your flops have to be
scanned, it can handle clocking data across a couple flops, then
scanning it out.)
But they still haven't told me how the heck I'm supposed to decide
what flops to scan and which not to. Or how to tell Test Compiler
that. Sure would be nice if Test_compiler knew what to do and I could
tell it: give me a capture depth of maximum 5. Oh well, someday maybe
we'll get half of the 20% area cost of scan back out.
You can tell Tmax a bunch of vectors you want applied to a block inside
your chip, and it will figure out how to turn those into scan vectors.
This has always been there, and if you can use a parallel test to get
there it's still prbably faster tahn scanning it in.
New features that take new licenses:
1. BSD Compiler: build JTAG logic automatically
2. Iddq vectors: create a vector that is "optimal" for Iddq testing
3. Transition delay vectors ATPG: cleverly make scan vectors look
like at speed tests, without having to pay for an at speed
tester. I didn't quite understand how that was possible, so
needs review if we care.
New in Tmax:
set drc -group_clocks
It's good, and it's not the default. Go figure.
Man, Tmax is cool. Somehow whoever made it convinced Synopsys that
they didn't have to follow Synopsys tool interface conventions. Thank
God for that. Test Compiler is a pain in the butt, I try to hit it
with kid gloves to get something out, and solve all my problems in
TetraMax.
For all you EDA guys out there, look to Tmax for an example of how
online help can be done - connected help to error messages, "What
should I do now" sections on every help page. It has some quirks,
but once you figure out the general way things work, all is well."
- Paul Gerlach of Tektronix
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