( SNUG 00 Item 7 ) --------------------------------------------- [ 4/05/00 ]
ANOTHER RELIGIOUS WAR REVISITED: The Verilog/VHDL SNUG'00 user stats
clearly give Verilog dominance in the North American market. When the
EuroSNUG'00 data comes in, this might be another story -- but since
Europe only accounts for 19 percent of the World EDA market (Dataquest),
it's not *that* much of a change in the story. The SNUG'00 user stats:
Only Use Verilog ########################### 54%
Use Verilog & VHDL due
to IP purchase/reuse
or another design team ######### 19%
Write RTL in VHDL,
Gates in Verilog ###### 13%
Use Both For Other Reason # 2%
Only Use VHDL ####### 15%
And the tools they used:
Synopsys VCS (Verilog) ################### 38%
Cadence NC-Verilog ############ 24%
Synopsys Vera ####### 15%
Synopsys VSS (VHDL) #### 9%
Cadence NC-VHDL ### 6%
Synopsys Covermeter ### 6%
ModelTech, which would probably have made a very good showing here, wasn't
in the survey because we were interested in the UNIX EDA used to design
the big chips. (When you're designing 0.18 um, 300 Mhz, 3 million gates,
you not using ModelSim and PCs no matter how nice you think the GUI is!)
"Ofek, Smith and Collett agreed that Verilog is here to stay, but
noted that VHDL is growing much faster. Collett predicted that the
VHDL and Verilog simulation markets will be roughly equal in 1994,
and that toward the end of the decade, the HDL market will be around
60 percent VHDL and 40 percent Verilog."
- Richard Goering, EE Times, May 2, 1994
"Not interested."
- an anon engineer on the new Synopsys Scirocco VHDL simulator
"Does Synopsys have any credibility with VHDL simulation? I'll believe
it when I see it. We've been using ModelTech/ModelSim almost
exclusively, despite owning dozens of VSS licenses."
- an anon engineer on the new Synopsys Scirocco VHDL simulator
"8:30 - 11:45 (WA5) Tutorial on Scirocco VHDL 9"
- the number of attendees at the Scirocco VHDL tutorial
"Right now, there's no real meat to SystemC, and yet we have to be
planning NOW for the next-generation verification methodology. So
SystemC is a Sword of Damocles which will chop off any residual interest
in dedicated verification languages like Specman and Vera, dooming them
all to orphan status, while itself remaining unrealized for the
foreseeable future. We'll be left with self-checking HDL benches or
C-language hacks for the next two years. Gack!"
- an anon engineer
"On Verilog versus VHDL: imagine all those years ago if we had one
language instead of two. Think if all that duplicated effort could
have been directed towards one language. How much further ahead would
we be today?"
- Aart de Geus, CEO of Synopsys, in his SNUG'00 keynote
"VHDL is one of the biggest mistakes the Electronics Design Automation
industry has ever made. A $400 million mistake. Wouldn't this money
have been better spent on handling submicron design, testability
issues, or even a new type of HDL that had significantly more
capabilities than what Verilog and VHDL offer today?"
- Joe Costello, then the CEO of Cadence, in his 1995 OVI keynote
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