( DVcon 05 Item 6 ) --------------------------------------------- [ 10/25/05 ]
Subject: the Future of Specman "e" and Vera
FUTURE DOOM -- Just like 2004, there's no way to sugar coat it in 2005; the
majority of engineers yet again see no future for Specman "e" nor Vera.
2004 - "Where do you think specialty functional verification languages be in
5 years? Dead or a growing part of the chip verification process?"
Dead : ######################################### 81%
Growing : ########## 19%
2005 - "Where do you think specialty functional verification languages be in
5 years? Dead or a growing part of the chip verification process?"
Dead : ####################################### 78%
Growing : ########### 22%
Of course there are always a few fanatics faithful to the old regime, but the
masses seem to see System Verilog as the future heir to the verification crown.
In 5 years, I think System Verilog will takeover, and both "e" and
Vera will be dead or dying.
- Dan Steinberg of Integrated Device Technology
Dead. System Verilog will eat them for breakfast.
- [ An Anon Engineer ]
Hard to $ay. It is very unlikely we will dump our inve$tment in
"e"-based tool$ in favor of anything el$e.
- Lyle Kraft of Agilent
Dead. Killed by System Verilog.
- Kea Hunt of Nazomi Communications
I think they are in the very early stages of a terminal illness. They
will continue to be heavily used for the next couple years, but System
Verilog will slowly replace them (especially Vera, since it is so
similar, and Synopsys is pushing users that way).
Five years from now there will still be people using their legacy Vera
or "e" code, but I doubt any new users.
- John Zook of Stargen
I think Vera and Specman "e" will be an indispensable part of the
design/verification process. Just like equivalence checking was
something optional some time ago, and now is a must. When complexity
grows, we need new paradigms and tools to go ahead.
- Juan Carlos Diaz of Agere Systems
I think those langages will continue to take a large part of the
verification environment in 5 years. I think System Verilog and "e"
will coexist, as VHDL and Verilog for design.
- Olivier Haller of STMicroelectronics
Dead.
- [ An Anon Engineer ]
System Verilog might kill these.
- Harish Bharadwaj of LSI Logic
My personal view is Specman/Vera are going to disappear.
- [ An Anon Engineer ]
Specman/Vera will both be dead as a separate tool. Part of simulation
package.
- Arun Chaddha of Tenesix, Inc.
Growing. HVL for sure is going to make inroads.
- [ An Anon Engineer ]
Dead and integrated into VHDL/Verilog RTL (like PSL will be).
- [ Kenny from Southpark ]
Vera will be dead for sure, since it will be replaced by System Verilog.
- Sylvain Boucher of Philips Semiconductor
Dead.
- Mark Lancaster of Freescale Semiconductor
I think E goes into a legacy status, still alive but not growing.
- [ An Anon Engineer ]
In 5 years, there will still be a need for verification languages.
System Verilog may satisfy some of the need but I don't buy the
argument that System Verilog will obsolete Specman. If that argument
was valid, Vera would have a greater marketshare than Specman today.
- Niels Reimer of Agilent
Dead. Native Testbench has better run-time performance than Vera.
- [ An Anon Engineer ]
I hope dead. I fear that they will take longer than that to die. I
think the industry would be better served if there were fewer HVL's.
All of this language stuff is annoying.
- Ian Perryman of Altera
In 5 years I expect to see Vera as a superset of System Verilog, and
the key "e" features as a superset of Cadence's offering. Unless
Verisity becomes another Ambit.
- [ An Anon Engineer ]
Dead!
- Sandro Pintz of Portal Player, Inc.
Dead. Probably see a mix of SystemC, System Verilog, and homegrown
C++. Simple economics driving that trend.
- [ An Anon Engineer ]
Synopsys Vera is definitely more powerful in terms of features, support
and methodology. RVM is definitely powerful addition to VERA/NTB.
In 5 years, I believe there won't be any Vera or SpecMan. There will
be System Verilog.
- Azeez Chollampat of PLX Technology
I looked at 'e' at the DATE in Munich, and I now understand why so many
people are using it. If Cadence does a good job after this Verisity
merger, I think it will be an ever growing part of the chip verification
process.
- [ An Anon Engineer ]
Vera becomes NTB becomes System Verilog in 5 years.
- Larry Davidson of Ario Data Networks
Dead
- Greg Tumbush of Starkey Labs.
I am using Specman. "e" will be growing like Perl is growing.
- [ An Anon Engineer ]
Growing
- Menno Lindwer of Philips Semiconductors
I'm no fan of closed proprietary solutions that could be dead next year.
- Christian Mautner of Integrated Device Technologies
Dead.
- William Mills of Northrop Grumman Corp.
DEAD. We never planned on using Vera beyond 5-6 years. Even back then,
Superlog appeared to have some momentum and we figured it was just a matter
of time. System Verilog will replace all of these languages as soon as its
stable and supported.
- Jonathan Craft of McData Corp.
Specialty languages will be dead if the Verilog body can get agreement
on System Verilog.
- [ An Anon Engineer ]
They'll be integrated in a 'container' language such as System Verilog.
- Stefano Traferro of STmicroelectronics
Vera will disappear once System Verilog is fully supported since most of
it comes from Vera.
For "e" it's hard to tell. I don't really see people who've got many
verification IP done in "e" moving away from it but on the other hand,
I don't really see new customers starting with "e".
- [ An Anon Engineer ]
I think that "e" and Vera will both be dead in 5 years. System Verilog
will dominate. I'm unsure if SystemC SCV will be a player in 5 years.
- [ An Anon Engineer ]
Dead - unless they open source them or make them extremely cheap...
- Tom Moxon of Moxon Design
Dead. The lack of a standard killed both "e" and Vera.
- [ An Anon Engineer ]
In 5 years, these verification languages will remain an important part
in the verification flow, maybe in the form of System Verilog.
- Peng Hong of Datang Microelectronics China
Probably Dead. If System Verilog has taken off by then.
- [ An Anon Engineer ]
No idea. I thought VHDL was going to take off, but Verilog went public.
- Ross Smith of NuCore Technology, Inc.
We think the Vera language will still be around in some form or
another, however we expect it to get blended into VCS/System Verilog
per Synopsys' plan (or at least what they are telling us).
- Tom Ebzery of Hifn, Inc.
I see both Specman and Vera being used in 5 years time, although some
managers will insist on using System Verilog for everything under the
misguided assumption that using one language will enhance productivity,
even if you can't do half the things you used to when using a
specialised verification language.
- [ An Anon Engineer ]
Dead as a doornail.
- Frank Vorstenbosch of Telecom Modus Ltd.
HVLs like 'e' and Vera are already being absorbed into System Verilog.
Does this kill them or give them immortality? [grin]
- [ An Anon Engineer ]
In my opinion speciality verification languages will go the way of the
dinosaurs and the new System Verilog verification extensions will
take their place.
- [ An Anon Engineer ]
Ever growing, of course. Verification languages have become too
important in the design process. Which specific languages will
survive I have no guess about. I include System Verilog as one of
the candidates.
- George Gorman of LSI Logic
System Verilog will dissolve them.
- [ An Anon Engineer ]
Dead
- [ An Anon Engineer ]
It will be an ever growing part of the chip verification process, but
will be integrated into System Verilog or other system level
modelling tool.
- Dave Ferris of Tundra Semiconductor
System Verilog will replace Vera.
Specman was at a disadvantage until it was bought out by Cadence
and merged with their simulator.
- Dan Joyce of Hewlett-Packard
Dead, as System Verilog will be the likely language of choice.
- [ An Anon Engineer ]
I see them incorporated into languages, like System Verilog.
- [ An Anon Engineer ]
Dead - Specialty languages have no future. SystemC should survive
since it can leverage enormous C++ knowledge base, tools, libaries.
- [ An Anon Engineer ]
Ever growing part of the chip verification process.
- [ An Anon Engineer ]
Vera in particular already morphing into System Verilog verification
extensions; I expect Vera to fade out over the next 2-3 years in
favour of an all-encompassing VCS. I'm not very happy about it;
unless ModelSim can support System Verilog verification extensions
to the same extent. I don't want to have to move to VCS.
- [ An Anon Engineer ]
Index
Next->Item
|
|
