( DAC'15 Item 9 ) ----------------------------------------------- [05/18/16]
Subject: ARM/SNPS/MENT rock IP survey while CDNS has embarrassing 2nd year
AN ACCIDENTAL RORSCHACH TEST: In 2014, was the first year in my DAC survey
where I asked a new question on what specific IP (hard/soft/VIP) engineers
used on their chips.
SURVEY QUESTION #2:
"What type of IP (hard/soft/VIP) INTERESTED you this year?
For what specific protocals/uPs/memories/standards?
What company made the IP you're interested in?"
And in 2014, 93 engineers repled on the IP question. In 2015, 156 engineers
replied. What else surprised me was that many of these responses came from
IP users who had not attended DAC. That is, because my survey questions
went out to ~40,000 DeepChip subscribers, it had accidently morphed into an
overall glimpse of what IP chip designers and verification engineer were
using worldwide -- regardless of if they attended DAC or not.
And yea, blah blah random sample blah blah, statical blah, blah, blah...
which is why I'm calling this a Rorschach test more than an "official"
survey -- it's their replies where you see the IP user's thinking!
---- ---- ---- ---- ---- ---- ----
ARM & SYNOPSYS KICK ASS: If you tabulate how many times what each engineer
had said about a specific IP/VIP vendor, it breaks out to:
something ARM: ##################################### 37%
something Synopsys: ################################### 35%
something Mentor: ########## 10%
something ImgTec MIPS: #### 4%
something SNPS ARC: #### 4%
something Sonics: #### 4%
something CEVA: #### 4%
something Cadence: #### 4%
something Arasan: ### 3%
something Dolphin: ### 3%
something TCI: ### 3%
something NanGate: ## 2%
something Kilopass: ## 2%
something Avery: ## 2%
something Sidense: # 1%
something Faraday: # 1%
something SiImage: # 1%
From this data, ARM (37%) plus Synopsys (35%) comprise 72% of what engineers
think of when asked an open question about IP/VIP. Mentor is the next lower
tier at 10%, followed by a roughly equal 4% or 3% splits of MIPS, ARC, CEVA,
Sonics, Cadence, Arasan, Dolphin, and TCI.
Making both Simon Segars of ARM and Aart de Geus of Synopsys as *the* two
big players in hard/soft/VIP chip IP -- followed by Wally Rhines of Mentor
as a distant runner up -- and with everyone else is in the noise.
---- ---- ---- ---- ---- ---- ----
CADENCE FALLS DOWN (AGAIN): Waaaay back in 2012 at CDNlive'12, Lip-bu Tan
had announced that he appointed Martin Lund from Broadcom to be his SVP
for all CDNS IP.
What was embarrassing was that even though Martin had Lip-bu Tan running
around telling Wall St. stuff fun quotes like:
"IP is a key component of our overall strategy and is now 12% of
our revenue, with growth last year of 17%."
- Lip-bu Tan, Cadence CEO, Q4 2015 CDNS earnings call
And his Susan Peterson, CDNS VIP marketing group director in 2012 claiming
that Cadence has "69% of the verification IP market" if you include Denali;
but when I did my first DeepChip IP survey last year, out of the 93 total
user comments last year on IP only 3 total were on Cadence IP/VIP!
When Martin saw this December 2014 news in DeepChip, he exploded and wrote
back in January 2015:
"John,
Since you seem so disconnected on what I do, let me school you on
the Cadence IP which I manage...
ARM AMBA 5 CHI, AMBA 4 ACE, AXI 3/4, AHB, APB, AMBA 4 Stream, CAN,
Display Port, Ethernet 10/100/1G/10G, Ethernet 25G/50G, Ethernet
40G/100G, HDMI 1.4, HDMI 2.0, I2C, JTAG/cJTAG, LIN, MHL 3.0, MIPI
CSI-2, MIPI CSI-3, MIPI C-PHY, MIPI DigRF, MIPI D-PHY, MIPI DSI,
MIPI LLI 2.0, MIPI M-PHY, MIPI SLIMbus, MIPI Sound Wire, MIPI UniPro,
NVM Express, OCP 2.2, OCP 3.0, PCI, PCIe Gen2, PCIe Gen3, PCIe Gen4,
PCIe SR-IOV, PCIe MR-IOV, M-PCIe, PLB 6, SAS 6G, SAS 12G, SATA 3G/6G,
SRIO 2.1, SRIO 3.0, UART, USB 2.0 w/ OTG, USB 3.0 w/OTG, USB SSIC..."
- Martin Lund, Cadence IP bigwig (ESNUG 546 #1)
Which triggered some 55 colorful DeepChip reader responses in ESNUG 547 #2.
But the story got weird not a few months after that when DAC 2015 happened.
As usual I ran my post-DAC survey in late June. I got a ton of responses;
but this time -- after all that grief Martin had given me -- the same lack
of Cadence IP or VIP customer responses happened again! WTF!!??? I ran
the survey again in September. Out of a total of 153 IP/VIP users replies,
there was only 1 Cadence VIP, 2 Denali, and 2 TenSilica responses!!! This
was the 2nd year in a row!! For a CDNS with 69% of the VIP market??! WTF!
Then Martin Lund resigned from Cadence to become the new CEO of Metaswitch!
And then Martin's old Cadence IP/VIP bigwig job (a 12% CDNS revenues job!)
had remained empty for 9 months until yet another Broadcom bigwig named
Pieter Vorenkamp quietly filled the SVP/GM IP role this May at CDNlive'16.
And when I say "quietly", I mean quietly. Cadence Corporate never issued a
press release saying Pieter Vorenkamp, one of only 10 CDNS executive staff,
had joined CDNS. (Talk about a painful IP story & rough entrance! Ouch!)
---- ---- ---- ---- ---- ---- ----
WALLY'S VIP ROCKS (AGAIN): For the 2nd year in a row, Wally's Questa VIP
(QVIP) was the most user commented VIP in this survey.
Questa VIP (QVIP) got 64% out of the all the "best of" VIP user mentions.
SURVEY QUESTION #2:
"What type of IP (hard/soft/VIP) INTERESTED you this year?
For what specific protocals/uPs/memories/standards?
What company made the IP you're interested in?"
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
VERIFICATION IP (VIP) COMMENTS: Mentor QVIP, Synopsys VIP, Avery VIP
Mentor Graphics Questa QVIP
The source code is mostly accessible to the user, which makes it easier
for debug and understand how to integrate.
---- ---- ---- ---- ---- ---- ----
Mentor QVIP. Both their PCIe and NVMe standards.
---- ---- ---- ---- ---- ---- ----
We currently use AMBA AHB and serial VIPs (I2C, SPI, UART, USB) from
Mentor Graphics. We are interested in AMBA AXI and CAN (which Mentor
has not provided yet) VIPs going forward. The features we like are
UVM, coverage, assertions, test plans and Mentor's willingness to
support our ramp up efforts.
---- ---- ---- ---- ---- ---- ----
We're looking for VIP and soft digital controller IP.
Seen a lot of improvement in the quality of Mentor VIPs this year.
Interested in PCIe Gen 3.0, MIPI DPHY, USB 2.0, DDR 4 & LPDDR4.
Not sure about the DDR4/LPDDR4 from Mentor as Cadence Denali is gold
standard here.
---- ---- ---- ---- ---- ---- ----
We have an SoC design that combines multiple IP using many standard
interfaces. On the verification side, we're using Mentor Questa VIP
for AHB and AXI today, and we're planning some additional protocols
from the Questa VIP library going forward. We mix UVM and straight
SystemVerilog testbench environments. We think that MENT's UVM VIP
architecture is solid, plus we like their protocol checking and
ability to output transactions to tracker files.
---- ---- ---- ---- ---- ---- ----
Our team focus is on the design and verification of a serial bus
physical layer, including PCIe, USB, MIPI, DP. Generally speaking,
we rely on VIP to verify our design. We've been using Mentor's
Verification IP team for this. Why we chose Mentor QVIP:
(1) QVIP supports UVM, which helps our testbench development.
(2) Even though we're not an Intel nor Apple, we get direct
support from Mentor VIP engineers directly, which clearly
helps us meet our schedule.
(3) Mentor R&D has their VIP stay up-to-date on latest standard.
This shorten our development time.
Hope this will be useful to you survey, John
---- ---- ---- ---- ---- ---- ----
Hi, John,
We use the Questa Verification IP from Mentor Graphics for display
and camera interfaces: MIPI CSI, DSI and DPHY, plus HDMI as well.
We like the common UVM architecture which makes QVIP easy to use
with VCS/Incisive/Questa simulators. But we like the QVIP hooks
that Wally's R&D put into Questa - we particularly like:
- the way transactions are displayed hierarchically in Questa
- the way QVIP assertions are displayed in Questa
- the way the testplans and coverage that come with each QVIP
are integrated into Questa verification management.
Also really like the fast support we get from Mentor when we have
any questions about their VIP.
---- ---- ---- ---- ---- ---- ----
We had some interest in the Mentor Graphics Questa VIP at DAC. We
are now starting to look at some of the Questa VIPs such as AXI,
memory models (NVMe), and MIPI in our IP Verification.
---- ---- ---- ---- ---- ---- ----
Mentor Graphics :
VIP for ARM AMBA AXI, APB, AHB protocols. We totally rely on them
for validating our IP.
---- ---- ---- ---- ---- ---- ----
MENT QVIP PCIE
It's a better alternative to ExpertIO.
And some IP from Altera.
---- ---- ---- ---- ---- ---- ----
DW for hard IP. QVIP to check it.
Having one rival verify the other is smart chip design.
---- ---- ---- ---- ---- ---- ----
We buy Mentor QVIP for testbench transactors and protocol monitors.
AMBA-APB, AXI3, AXI4-Streaming, ACE DDR3/4.
For memory VIP we use Cadence-Denali
---- ---- ---- ---- ---- ---- ----
Questa QVIP for our HDMI 2.0 Tx and Rx blocks
---- ---- ---- ---- ---- ---- ----
Synopsys VIP for the AMBA 5 CHI protocol
---- ---- ---- ---- ---- ---- ----
We use mostly SNPS VIP because it comes in the DW bundle.
---- ---- ---- ---- ---- ---- ----
Synopsys AXI IP and VIP
---- ---- ---- ---- ---- ---- ----
My focus is on VIP setup and usage. We use Cadence PCIe and AXI VIP.
---- ---- ---- ---- ---- ---- ----
Our Mentor sales guy says Mentor QVIP is the market leader.
Our Cadence sales guy says Cadence VIP is the market leader.
Our Synopsys sales guy says Synopsys VIP is the market leader.
Two are lying. But which two?
---- ---- ---- ---- ---- ---- ----
SmartDV: vip for AMBA5 CHI and DDR4
---- ---- ---- ---- ---- ---- ----
Hard IP: Synopsys DW USB 3.1
VIP: Avery Design USB-Xactor in SV and UVM
---- ---- ---- ---- ---- ---- ----
Avery 3D Stacking DDR4 LRDIMM compliance testsuites
---- ---- ---- ---- ---- ---- ----
Avery DDR-Xactor DDR4/3 vip
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
HARD IP COMMENTS: Synopsys Designware, ARM, Ceva, Arasan
I don't think it's possible to run Design Compiler without at least
the basic DesignWare library as part of its mappings.
---- ---- ---- ---- ---- ---- ----
DC defaults to DW
---- ---- ---- ---- ---- ---- ----
We hand instantiate most of our DSP architecture from the Synopsys
floating point DesignWare components and then dont_touch them. They
have a fairly extensive list of parts to choose from.
---- ---- ---- ---- ---- ---- ----
many DW Adders and multi-staged Multipliers in fixed point datapath
---- ---- ---- ---- ---- ---- ----
This year I became the company expert in the DW CDC parts lib.
I can tell you everything and anything about any DW_****_sync or
DW_****_qsync component. DO NOT TRUST CTS WITH THESE PARTS!
---- ---- ---- ---- ---- ---- ----
Loose DW flip-flops, DW boundry scan, and the DW TAP controller
---- ---- ---- ---- ---- ---- ----
DW
---- ---- ---- ---- ---- ---- ----
For hard IP: DW
---- ---- ---- ---- ---- ---- ----
Designware
---- ---- ---- ---- ---- ---- ----
That crap IP that comes built into DC-Graphical
---- ---- ---- ---- ---- ---- ----
Floating Point DW
---- ---- ---- ---- ---- ---- ----
lots and lots of DW FIFO's everywhere
---- ---- ---- ---- ---- ---- ----
I think DW, but don't know if it's hard or soft IP.
In RTL synth DC tweaks DW a lot.
---- ---- ---- ---- ---- ---- ----
We use both DesignWare hard IP and VIP for our SoC's.
---- ---- ---- ---- ---- ---- ----
Mostly DW and ARM for our hard IP.
---- ---- ---- ---- ---- ---- ----
Aart has over 100 DW building blocks that we've been using
for decades. He was smart to do that.
---- ---- ---- ---- ---- ---- ----
We're looking at the different DesignWare AMBA fabrics now
---- ---- ---- ---- ---- ---- ----
DW interconnect fabric for AMBA 3 AXI and AMBA 4 AXI
---- ---- ---- ---- ---- ---- ----
Current chip uses DW AMBA 4 AXI
---- ---- ---- ---- ---- ---- ----
designware
---- ---- ---- ---- ---- ---- ----
DW Foundation
---- ---- ---- ---- ---- ---- ----
Synopsys AMBA 3 AXI DMA Controller
---- ---- ---- ---- ---- ---- ----
We looked at CoreAssembler years ago but didn't buy it
---- ---- ---- ---- ---- ---- ----
DesignWare USB 3.0, DDR, MIPI, and basic IP
---- ---- ---- ---- ---- ---- ----
DW USB 3.0, DW LPDDR3/2 and DW MIPI D-PHY IP
(It came as a package for us.)
---- ---- ---- ---- ---- ---- ----
DW USB 3.0, AXI4
---- ---- ---- ---- ---- ---- ----
Sibridge USB 3.0 host & device
---- ---- ---- ---- ---- ---- ----
Synopsys has a pretty good USB 3.0 controller we use
---- ---- ---- ---- ---- ---- ----
We're comparing Arasan USB 3.0 core vs. Designware USB 3.0 core
---- ---- ---- ---- ---- ---- ----
Designware HDMI 2.0 TX & RX
---- ---- ---- ---- ---- ---- ----
DW HDMI 2.0 & USB 3.0
---- ---- ---- ---- ---- ---- ----
Analogix HDMI 1.4 Transmitter IP
---- ---- ---- ---- ---- ---- ----
I heard Mentor has HDMI cores in the works.
---- ---- ---- ---- ---- ---- ----
Silicon Image HDMI 2.0 SiI9779
---- ---- ---- ---- ---- ---- ----
Was SiliconImage for HDMI 1.4; now for 2.0
---- ---- ---- ---- ---- ---- ----
Silicon Creations SerDes UMC 28nm
---- ---- ---- ---- ---- ---- ----
CEVA-SATA3 AHCI Host Controller
---- ---- ---- ---- ---- ---- ----
Ceva sata
---- ---- ---- ---- ---- ---- ----
CEVA-SATA3 Device Controller (6Gbps)
good NCQ acceleration
---- ---- ---- ---- ---- ---- ----
Ceva WiFi IP 802.11n 802.11ac 2x2
---- ---- ---- ---- ---- ---- ----
DesignWare SATA Controller and PHY IP
---- ---- ---- ---- ---- ---- ----
We use a lot of third party IP. We are mostly interested in
SerDes & high speed interface IP. Both Cadence and Synopsys
have solid portfolios in this area. Although we use mostly
Synopsys DesignWare and the Verdi Protocol Analyzer, it is
good to see Cadence putting more emphasis on IP.
This has been a Synopsys monopoly for too long.
---- ---- ---- ---- ---- ---- ----
Arasan Ethernet MACs & ARM cores
---- ---- ---- ---- ---- ---- ----
Arasan MIPI D-PHY TSMC 28nm HPM
---- ---- ---- ---- ---- ---- ----
We use Mixel for MIPI IP
---- ---- ---- ---- ---- ---- ----
Synopsys HAPS, DW MIPI, ARC
---- ---- ---- ---- ---- ---- ----
a wide array of Synopsys MIPI and USB IP
---- ---- ---- ---- ---- ---- ----
Veriest MIPI
---- ---- ---- ---- ---- ---- ----
Faraday MIPI FTDSIP100
---- ---- ---- ---- ---- ---- ----
We are shopping for GPIO TSMC 16FF+ IP. Either Dolphin or DW.
---- ---- ---- ---- ---- ---- ----
ARM has a bluetooth IP available: Cordio - a new debut into
the mixed signal RF IP world for them? (Disclosure I know the
director in ARM but I didn't know what they were working on
for the last couple of years until this DAC.)
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
STD LOGIC LIB & MEM COMPILERS: Synopsys Designware, Dolphin, Nangate
We're interested in the Synopsys Samsung 10LPe memory compilers
---- ---- ---- ---- ---- ---- ----
DesignWare TSMC 28HPC/HPC+/HPM logic and memory compilers
---- ---- ---- ---- ---- ---- ----
Using DW UMC 28nm logic library
---- ---- ---- ---- ---- ---- ----
We use DW std cell libs everywhere
---- ---- ---- ---- ---- ---- ----
We're ARMH for std libs and memories. 16nm --> 10nm
---- ---- ---- ---- ---- ---- ----
ARM TSMC 16nm CLN16FPLL001
1200 cells per Vt.
---- ---- ---- ---- ---- ---- ----
Cortex A9 plus Artisan SC12 std cell lib
---- ---- ---- ---- ---- ---- ----
TowerJazz 65nm standard cells. Our chip is very cost senstive.
---- ---- ---- ---- ---- ---- ----
ARM CoreLink DMC-500 to LPDDR4/3
---- ---- ---- ---- ---- ---- ----
NanGate released a 15nm open cell library.
Who has a 15nm foundry?
---- ---- ---- ---- ---- ---- ----
The NanGate Library Creator looks interesting, but they stopped
at 22nm. If they did 16nm or 14nm, I'd be interested.
---- ---- ---- ---- ---- ---- ----
NanGate
They have some interesting std cell lib creation ideas.
---- ---- ---- ---- ---- ---- ----
Looking at NVM IP. Kilopass, Sidense, Synopsys DW Aeon
---- ---- ---- ---- ---- ---- ----
We have 8K security keys everywhere. Kilopass XPM NVM 16nm.
---- ---- ---- ---- ---- ---- ----
Kilopass Gusto 28nm TSMC HP/HPM is best because portable
between foundries.
---- ---- ---- ---- ---- ---- ----
Sidense SHF 1T-OTP technology looks interesting.
---- ---- ---- ---- ---- ---- ----
Dolphin TSMC 16FF+ std cell lib
---- ---- ---- ---- ---- ---- ----
Dolphin makes fairly OK 28nm SRAM compilers
---- ---- ---- ---- ---- ---- ----
Dolphin TSMC 28HP 10-track std lib
---- ---- ---- ---- ---- ---- ----
Why we have to pay Synopsys for quality logic and memory
compilers? The TSMC ones are primative. Shouldn't TSMC
provide good ones as part of their PDK?
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
PROCESSOR CORE IP: ARM Cortex, ImgTec MIPS, Designware ARC, Ceva
We're an old 90nm node company for a/D IoT chips. R&D plus
licensing cost is paramount for us. All we needed was either
16-bit or 32-bit RISC. Took that deal last year where ARM
fast track licensed Cortex-M0s for $40K. Only ~16K gate
footprint on our chip. Best move ever for us. They even
threw in an Altera Cyclone V prototyping board (150k gates)
for $1.2K.
---- ---- ---- ---- ---- ---- ----
Quad Cortex A57 + A53, Mali MP8, LPDDR4 + DW Foundation
---- ---- ---- ---- ---- ---- ----
ARM A-72
---- ---- ---- ---- ---- ---- ----
64 bit ARM cores
DW USB 3.1, MIPI
Mentor QVIP
---- ---- ---- ---- ---- ---- ----
ARM Trustzone has been big for us this year.
---- ---- ---- ---- ---- ---- ----
I like seeing the ARM Pavillion at DAC.
---- ---- ---- ---- ---- ---- ----
We're all ARM and DesignWare here.
---- ---- ---- ---- ---- ---- ----
Our design went Cortex-A9 to Cortex-A15.
32-bit works. Especially with the 40-bit LPAE.
---- ---- ---- ---- ---- ---- ----
ARM cores
---- ---- ---- ---- ---- ---- ----
Cortex A12. Oops, make that Cortex A17. They renamed it.
---- ---- ---- ---- ---- ---- ----
ARM M0 (we're cheap)
---- ---- ---- ---- ---- ---- ----
DW + ARM
---- ---- ---- ---- ---- ---- ----
We do SSD's so Cortex-R7. Considering their R8.
---- ---- ---- ---- ---- ---- ----
32 bit ARM is enough for us
---- ---- ---- ---- ---- ---- ----
M0
---- ---- ---- ---- ---- ---- ----
Cortex A53 quad, DesignWare USB 3.0, PLDA PCIe 4.0 16Gbps
---- ---- ---- ---- ---- ---- ----
ARMH
---- ---- ---- ---- ---- ---- ----
Our chips are DSP. ARM Cortex M4.
---- ---- ---- ---- ---- ---- ----
it's cortex something
---- ---- ---- ---- ---- ---- ----
ARM Mali T880MP12, 4x A53
---- ---- ---- ---- ---- ---- ----
SC000 32-bit AHB-lite, PL061 GPIO
---- ---- ---- ---- ---- ---- ----
A57's and A53's
---- ---- ---- ---- ---- ---- ----
Saw a lot of ARM in the TSMC and Cadence boths.
ARM-TSMC-Cadence seems to like each other.
---- ---- ---- ---- ---- ---- ----
Socrates ARM and IP-XACT still doesn't work.
---- ---- ---- ---- ---- ---- ----
We buy ARM because ARM falls all over themselves with amazing
customer support and we're not a big Tier 1 account.
---- ---- ---- ---- ---- ---- ----
ImgTec Warrior I6400
MIPS 64-bit but bkwds compatible with MIPS 32-bit
256-bit internal dp's, 4 threads per core
can do 256 hardware interrupts
---- ---- ---- ---- ---- ---- ----
My mgmt likes MIPS CPUs because they're significantly cheaper.
---- ---- ---- ---- ---- ---- ----
Imagination MIPS
Simple coding syntax
Two operating modes
Pure RISC -- less # of instructions
Memory stack grows downwards
No conditional bits -- needs branch instractions
32 registers that are 32-bit wide
5 mem addressing modes
Their new OmniShield is alpha rev of TrustZone security equivalent
Low power
No virtualization
Good customer support
Updates 1X or 2X per year
PRPL is their open source version of architecture
No company marketing, relies on engineers to find about them on own
Simpler core and architecture overall -- strong for IoT
Very low cost. 1/3rd price of eqvlt ARM cores
ARM Cortex
Complex coding syntax
Nine operating modes
Moderate RISC -- higher # of instructions
Memory stack grows both downwards and upwards
Has 4 conditional flags -- Z, V, C, N
16 registers that are 32-bit wide + 12 GP registers
4 mem addressing modes
Has mature TrustZone security
Low power
Virtualization
Exceptional customer support
Updates 1X or 2X per week
No open source, it's all proprietary architecture
Ubiquitous corporate marketing everywhere at all times
Complex core and architecture overall -- strong for mobile
Premium pricing. 3X price of eqvlt MIPS cores
---- ---- ---- ---- ---- ---- ----
PowerVR Rogue GE8300 4px/clock OpenGL 3.3
---- ---- ---- ---- ---- ---- ----
Here's a pic I shared with my colleagues from the ARC Summit,
John. Please use the data but keep the pic private.
Linley Gwenapp reported at the Synopsys ARC Summit that in
2014 15.3 billion chips were shipped with these cores:
ARM ###################### 72%
Synopsys ARC ### 11%
Imagination MIPS # 5%
Cadence Tensilica # 4%
Linley forecasts a CAGR of 13% through 2018 for all cores.
28nm is the sweet spot for cents/transitor.
Aart de Geus predicts IoT is the next wave. Says he ships
1.7 billion chips/year with ARC cores at ~2.5-3 cores/chip,
making ~4 billion ARC cores/year.
---- ---- ---- ---- ---- ---- ----
IP protocols: MIPS, USB 3.0, MIPI
IP suppliers: Imagination, Arasan, Designware
---- ---- ---- ---- ---- ---- ----
ARM Cortex M4 or Synopsys DW ARC EM cores
Both are low power 3-stage pipelines CPUs with DSP added.
DW ARC EM cores are configurable. You can delete registers
and other hardware you don't want. Makes the ARC silicon
footprint 1/2 the size of M4 footprint. Both have lite DSP.
Cortex-M4s are very popular. Online choice of at least
50 brands of ARM Cortex development boards at $15 to $150.
Also hundreds of 3rd party software apps. Can even buy
builds for Android. There are many large online ARM user
communities around.
Designware ARC has only been licensed 200 times. Synopsys
makes and sells the only ARC development board available
for $200. There are no 3rd party software apps for ARC.
No online user community. It's emBARC web site is dead.
DW ARC EM cores sell at ~1/2 price of ARM Cortex-M4's.
We have some IoT chips in the works.
---- ---- ---- ---- ---- ---- ----
SNPS DW ARC EM7D at 60% of the price of M4s.
---- ---- ---- ---- ---- ---- ----
Since all we needed was a 32-bit general purpose CPU on our
next design, we had both Synopsys and ARM put in bids. The
Designware ARC bid was 1/2 of ARM's. The ARM saleman was
furious.
---- ---- ---- ---- ---- ---- ----
For this year the Synopsys embARC.org web site for DW ARC
open software developement is the biggest lie.
It's tightly controlled by Synopsys marketing. You can't
register unless your email address is from a Synopsys
approved customer domain.
---- ---- ---- ---- ---- ---- ----
I was impressed at Hot Chips Symposium by Fujitsu XIf.
34 SPARC64 core 2.2GHz doing 1.1 Tera flops. It used
hybrid memory cubes (HMC) to get 30 Gbytes/sec throughput.
---- ---- ---- ---- ---- ---- ----
CAST BA25 in two AXI4 64-bit busses
It's small. 200k gate footprint in 45nm
---- ---- ---- ---- ---- ---- ----
2. Our interest is in configurable processors and ASIPs.
Cadence Tensilica,
Synopsys ARC/ASIP Designer,
Codasip Codix/Codasip Studio.
---- ---- ---- ---- ---- ---- ----
Cadence Tensilica Xtensa (for an upcoming SOC processor platform).
---- ---- ---- ---- ---- ---- ----
We want fast and cheap: CEVA-TeakLite cores
---- ---- ---- ---- ---- ---- ----
Pricing out vision processors like CEVA-XM4 and CEVA-MM3101
---- ---- ---- ---- ---- ---- ----
Vivante GC400 OpenGL ES 2.0 core
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
NETWORK-ON-CHIP (NOC) COMMENTS: Sonics SGN or ARM CoreLink
Our chip is simple. TSMC 28LP
SonicsGN, four ARM Cortex A17, DDR4, DW USB 3.0, DW MIPI
---- ---- ---- ---- ---- ---- ----
SGN
---- ---- ---- ---- ---- ---- ----
Sonics SGN
It sockets well to AXI4 parts and LPDDR4 memories
---- ---- ---- ---- ---- ---- ----
SonicsSX. Our chip needs that crossbar switch.
---- ---- ---- ---- ---- ---- ----
Sonics NoC. I can't remember its exact name.
---- ---- ---- ---- ---- ---- ----
SonicsGN plus some ARM core plus many a Designware block
---- ---- ---- ---- ---- ---- ----
ARM Cortex A72, A53, CoreLink NIC 450
---- ---- ---- ---- ---- ---- ----
ARM CoreLink CCI-500. Need cache coherency everywhere.
---- ---- ---- ---- ---- ---- ----
I got in an extended discussion with an ARM engineer at their
DAC pavilion about the differences between CCI-400, CCI-500,
and CCI-550 interconnect schemes. Can't remember his name.
---- ---- ---- ---- ---- ---- ----
Arteris didn't show at DAC this year. Janac still rebuilding?
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
FPGA IP: AdicSys eFPGA or Menta Origami
AdicSys is a synthesizable pragrammable FPGA core that's
embedded into your std cell ASIC. An FPGA block inside
your SoC for your later functional ECO's. Fully digital
PnR. No need for tweaks in Virtuoso. No Virtuoso needed.
Mostly for TSMC 28nm, but some Samsung/GF 14nm.
They're based outside of Paris, France.
---- ---- ---- ---- ---- ---- ----
Menta is a French company with embedded programmable logic
IP (called "eFPGA's") for use in ASICs. Their Origami
eFPGA's are composed of embedded Logic Blocks (eLB),
embedded Customer Blocks (eCB) or embedded Memory Blocks
(eMB). TSMC 28HPM, STM 28FDSOI and GlobalFoundries 14LPP.
---- ---- ---- ---- ---- ---- ----
Two French companies selling embedded FPGAs at DAC? Two?
---- ---- ---- ---- ---- ---- ----
Menta?
That's like calling a new OS software company "Microsof" to
compete with Microsoft.
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
PLL Clock Tree IP: TCI, Analog Bits, Faraday
Have you seen the True Circuits Inc web site?
It lists a few hundred PLL/DLL IPs they have in stock.
---- ---- ---- ---- ---- ---- ----
TCI CLN16FF+ 3.5G
---- ---- ---- ---- ---- ---- ----
TCI Inc.
---- ---- ---- ---- ---- ---- ----
UMC PLI L28HLP PLLs
---- ---- ---- ---- ---- ---- ----
Analog Bits Fractional-N PLL - TSMC 28nm CLN28HPC
---- ---- ---- ---- ---- ---- ----
Analog Bits PLL
---- ---- ---- ---- ---- ---- ----
Faraday has some competitive 28nm PLLs.
---- ---- ---- ---- ---- ---- ----
Related Articles
ARM, Synopsys DesignWare, Mentor VIP, but Cadence IP went missing?
Join
Index
Next->Item
|
|
