( DAC'15 Item 5 ) ----------------------------------------------- [11/05/15]
Subject: Calypto Catapult HLS beats Cadence Stratus for #5 tool at DAC'15
AND THEN THERE WERE TWO: This was a killer DAC for Calypto Catapult HLS.
They had Google openly using Catapult last year before the show.
This year they had Nvidia, Qualcomm, and ST chatting up Catapult 8.0 HLS on
real chips that were actually sold in real products. (And my spies told me
that Broadcom was just about to buy a boatload of Catapult licenses.)
In contrast, the Cadence Stratus/Cynthesizer/C-to-Silicon users seemed to be
a bit more surly and questioning -- especially about Stratus being "new" SW
instead of repackaged Forte Cynthesizer.
And I've had sources tell me that SNPS Synphony C has been end-of-lifed (see
ESNUG 552 #1), but Synopsys Corporate won't return my calls on this.
From user comments, Catapult 8.0 HLS clearly "won" the C-to-RTL synthesis
niche at DAC this year.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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I went by Calypto's booth and sat through couple of Catapult customer
success stories.
Our group is interested - we've already scheduled internal training.
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Our design teams are now experts on Calypto Catapult HLS. Using a
high abstraction level has some advantages:
- At the IP level it drastically eases functional development
and verification needed by providing a more readable chip
description and a 1000x simulation speed.
- We can explore/rework microarchitecture with marginal effort.
- Catapult offers a SystemC TLM view of our IP which can be used
for integration of virtual prototypes. This the lets software
guys and the verification engineers do pre-silicon development;
so we can demonstrate key system functions within a few days
after silicon.
We use Calypto in our development flow for areas where it's relevant.
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Calypto's presentation at DAC on Catapult HLS was great.
They've made progress in the last couple of years. The "C-based
high level design flow" is what people will use in the future.
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I attended a Catapult HLS Qualcomm presentation at the Calypto booth.
Based on that presentation it is clear that the HLS technology has
matured to the point where it is now being used for critical design
blocks. I have been following HLS technology for over 8 years.
This was one of the few presentations where I was able to understand
this from a customer's (Qualcomm) perspective. The benefits:
- The ability to code at a higher level of abstraction results in
much smaller code -- reducing the probability of errors.
- You can easily evaluate multiple architectures by changing the
latency constraints. The Catapult customer was clearly able to
take advantage of these features in their design flow.
HLS may not be useful for every ASIC, but there are clearly datapath
oriented designs where it can be help.
To further accelerate C-based design adoption, we need formal (and
informal) verification to catch up.
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My feedback on Catapult HLS is for C++ design only.
Catapult HLS Pros:
It's generated RTL is a huge improvement in QoR since Catapult v8.0,
comparing to the old v2011a -- especially in terms of coding style
and friendly to clock gating insertion.
I've witnessed up to ~40% in power savings.
In my experiment:
- v8.x generated RTL in on-par vs. hand-written RTL in area,
timing, and power
- Great tool for micro-architecture exploration
- Quick algorithm-change-to-RTL-synthesis-report iterations
is now in hours -- compared to otherwise weeks/months of
work in hand-written RTL design flow
Catapult HLS Cons:
ECOs are not practical at this moment, though Calypto claims they
are working on improvements along with new version releases. BTW,
the Calypto Catapult presenter from Qualcomm said they haven't done
a single ECO for 8 years of usage - that amazed me!
Pure C++ HLS is limited to unit/engine level. It is not a suitable
tool for system-level modeling.
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Catapult HLS. A full flow, including verification, equivalence
checking, and implementation.
I was surprised that their HLS methodology could now be adopted
for a sub-system instead of only one module.
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Calypto Catapult HLS seems extremely capable.
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Catapult is still the most user friendly HLS tool. They had a good
customer presentations at DAC. The micro-architectural exploration
and SystemC vs. C++ topics were also very helpful.
However, it's still hard to make a switch from the other HLS tools
(Cadence Stratus and Cynthesizer) we are currently using.
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Catapult HLS. I attended both the NVIDIA and Qualcomm presentations
at DAC. I was impressed by the adoption of a third-party HLS tool
in both companies.
Of course, this may not be a big trend, but now we have chips on
the market made with Catapult HLS. (Similarly I saw other chip
companies present their experience with Cadence HLS tools.)
In all of these cases, HLS delivered what it promised:
- to meet time-to-market, and
- to allow an earlier verification of the system
There is still work to do. NVIDIA designed small functionalities at
a higher level of abstraction. Qualcomm showed early verification
of a C design that had nonequivalence checking between C and RTL.
In any case, I am positive for the future of C-based chip design.
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Catapult HLS
It seems to work better for Algorithm/Architecture-level design.
For the SOC implementation, it cannot replace RTL development.
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Calypto solves a very small part of the SOC synthesis puzzle with
its Catapult tool. It does only one algorithm at a time, and that
is only after significant manual intervention.
Long way to go before a quantum leap over what can be done at RTL.
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Calypto SLEC
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Calypto SLEC
What use is C-to-Verilog RTL if you can't be sure it's true?
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CADENCE STRATUS HLS COMMENTS
I liked Stratus HLS because it takes in untimed C.
Call me a purist, but only untimed C is true C design.
Everything else is a Verilog wannabe.
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CDNS Stratus looks an awful lot like Cynthisizer with some SW
wrappers put around it.
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That Stratus or C-to-Silicon crap is crap.
Real designers don't design hardware in C.
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Stratus HLS seemed well suited for SoC's that have to be in
the market very very quickly; which is us.
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In the Cadence Stratus demo the Cadence presentor would only
mention Genus or that "other RTL synthesis tool." Couldn't
say the words "Design Compiler" whatsoever.
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No SNPS Synphony C tool at this DAC. You might be right that its
discontinued.
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Related Articles
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Calypto Catapult beats Cadence Forte/C2S for #3 tool at DAC'14
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