( DAC 11 Item 8 ) ----------------------------------------------- [10/13/11]
Subject: Analog Rails, Magma Titan ADX, Springsoft Laker, Cadence Virtuoso
MAY I HELP YOU? Looks like "fully automated" and "assisted" were the two big
catch phrases in analog layout this year. The top in this category is a
small start-up based in Arizona called "Analog Rails", run by the ever
cantankerous Cliff Wiener. Know for his occasional gaffes, it appears
Cliff now has some *serious* analog users looking at his tools this year.
NEW TOOLS -- Analog Rails Mr. Fixit automatically repairs layout, both
DRC and LVS. Placer generates layouts of ADC, SC-Filters, biases, and
digital. "Automatic! No scripting needed!" Router is electrically
aware, handles EM, shields, double vias, welltaps. Layout Editor
crossprobes even when flattened. Optimizer does auto xistor sizing.
Mismatch tool does variation-aware. Also has IR-drop and migration.
(booth 1631) Ask for Cliff Wiener. Freebie: Cliff's surly attitude
- from http://www.deepchip.com/gadfly/gad060211.html
Magma Titan ADX and Springsoft Laker got some honorable mentions in
automated/assisted, also. I don't know why no one mentioned Ciranova Helix
this year, though. Maybe because it uses PyCells instead of Pcells?
"What were the 3 or 4 most INTERESTING specific tools that
you saw at DAC this year? WHY where they interesting to you?"
---- ---- ---- ---- ---- ---- ----
Analog Rails - Demonstrated a very tight link between schematic entry
and layout placement. Both their schematic entry and layout tools are
custom products but read and write out to OA. Various constraints
can be placed on the schematic and these are reflected in the layout
placement. The layout parasitics are then directly back annotated onto
the schematic for simulation without having to go through the whole
design, placement, extraction flow; which is one of the largest issues
when you get to smaller geometries in analog design. This is quite a
radical change in thinking but seems to deserve attention.
- Chris Geen of Analog Devices, Inc.
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Analog Rails because there is a real link on-the-fly between schematic
and layout windows. This link allows designers to generate a layout
corrected-by-construction avoiding DRC and LVS runs. It seems to be
very useful for AMS IP porting process.
- Pierluigi Daglio of STmicroelectronics
---- ---- ---- ---- ---- ---- ----
Analog Rails: revolutionary aproach to an old story. Might be especially
useful for fast analog prototyping and concept/architecture exploration.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
Analog Rails has to be it because they're doing true automatic analog
PnR with DRC-correct routing. Floorplanning, auto dummy fill, PCells,
differential PCells builtin. Places mosfets, fringecaps, mimcaps,
resistors, bipolars. Uses extracted values. Added MSIM and 180 nm to
65 nm migration this year.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I attended a demo for Titan ADX at the Magma booth at DAC.
This is their analog design tool that performs optimizations of designs
based on equations as opposed to simulation. The idea is that for each
building block in the design, which are called "FlexCells" in Magma
terminology, there is a set of parameterized equations that are used to
describe the behavior of your analog design's key metrics. These
parameters could be transistor sizes, resistor and capacitor values, etc.
When a design objective is specified, ADX will analyze the design and
determine the set of parameters that is optimized for your objective.
What's attractive is that ADX comes with a library of building blocks;
so the tool is ready to use off-the-shelf as you can use these as the
starting point for your analog designs.
Since ADX is based on equations, its run time is much faster than similar
simulation-based analog tools. Of course, the caveat is that any tool
is only as good as what you feed into it. So the quality of the results
depends very much on the library of FlexCells and the equations used to
describe them, as well as how the design objectives are specified.
Nevertheless, with the scarcity of automated analog tools out there, this
one is a useful addition to your toolbox, but must be used with care.
- [ An Anon Engineer ]
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Springsoft - Laker family of products is coming up with a kick-ass placer
for analog. Using architecture exploration ideas, the tool generates
multiple solutions and you can continue down the path from a chosen one.
Same "thinking" as Cadabra had when it was in glory times.
Start a family of designs and chose a path until happy or infeasible
then you can turn back and start from a different design. You can add
guard rings, change finger size, apply ECO, etc. When ECO applied you
have again local options based on the starting topology. I think that
after CCT creation of IC Craftsman, this is the closest to what a
designer needs to explore analog, assisted not automated. Router is
in the works but if the result is close to what the placer features are;
a great environment for analog is shaping up in full compliant OA...
Springsoft - Laker family again - a schematic driven place and route for
full custom libraries. We all know that Pulsic has the greatest tool
here, including clock tree EM/IR, but in many cases a good enough but
lighting fast is what makes the day. The tool is called CDPR - Custom
Design Place and Route and can do almost everything, power rails, filler
cells, etc. No CTS and no timing but this is not the segment they are
trying to fit in. The price is probably a portion of a full P&R but is
covering the niche market of peripheral circuitry for memories, small
digital blocks within analog structures. The advantage is that is OA
and teamed up with Laker polygon pusher can do a lot today... Also router
is DFM compliant at 28 nm, based on ALPS data coming from foundries !
Cadence - LEA starts to gain ground. Layout Dependent Effects or LDE
are an important part of quality of layout in 28 nm and below. The tool
can show what you leave "in performance on the table" by analyzing the
layout versus design constraints. I can see more tools like this coming
up in the next while... So when you have differential, symmetrical,
devices you can find how much of your transistor size, Vt, IdSat, is
different based on WPE, LOD, etc... If you need balanced circuits, if
you need to squeeze the last drop out of a device performance a tool
like this is a must.
Cadence - MODGEN gets rounting in 6.15. After almost 10 years MODGEN
(the hierarchical PCELL) created originally by NeoCell as polygons,
migrated later to PCELL now get back the feature that includes
local routing. The advantage is that if you have a team of experts (!)
they can create templates for symmetrical devices, centroids, current
mirrors, etc. Once all is in template based with all the routing, the
layout person using Virtuoso can drag and drop from schematic the
perfect template for the job (performance, area, symmetry, etc.) and it
was already calibrated by the technology access team, or your experts.
Add to this LEA and is the perfect Analog in 28 and below.
Cadence - answers last year's Laker+Calibre initiative by putting
Virtuoso+PVS together. The advantage is that you use the tool online,
batch mode online and GDSII level so compatibility should not be an
issue. The small problem is that like in Laker case you need a full
size verification engine attached to a polygon environment. 5k layout
+ 100K verification = 105k a seat for layout basics, kind of expensive.
I am sure that Mentor as well as Cadence are working on a "verification
light" version of the tools to provide an incentive to use these
features. Maybe at 5-10k a light license there is a business case, at
105k I don't see the future of this feature.
Synopsys - SmartFix - an online tool that runs in Custom Designer
environment and show errors related to DRC (like Cadence DRD) but at a
push of a button can also fix them... Fast, useful and even so is not
signoff perfection will save a lot of time in verifications. Cadence
is still working on a solution here...
- [ An Anon Engineer ]
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Magma Titan shape-based router. For connecting busses between blocks
(digital and analog) and completing river routes clean. The analog
database can be brought in from Cadence OA and the digital database is
in Talus Volcano. They are also working on automatically figuring
out if and when routes need to be buffered to prevent loss of signal.
- [ An Anon Engineer ]
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