( DAC 04 Item 6 ) ---------------------------------------------- [ 02/09/05 ]
Subject: Synplicity Synplify Pro and Synplify ASIC
IN TWO BAR FIGHTS -- In the FPGA synthesis market, Synplicity is in a bar
fight with Mentor Exemplar/Leonardo/Precision for the few paying customers.
In the ASIC synthesis market, Synplicity has the balls to take on the
Synopsys monopoly there. Fighting a war on two fronts! Scrappy!
Synplify is an easy-to-use tool, it gets the job done. Haven't used
Exemplar for a spell but it worked well when I did. When I am working
on an ASIC I use DC, but when working on an FPGA Synplify is my tool
of choice.
- [ An Anon Engineer ]
I've been using Synplify-Pro for approximately for 3 years now. It's
fast, relatively easy to use. Nice to see Gated Clock conversion is
becoming mature. Could be more extensive support for scripting.
Verilog relative search path does not match the relative source file
search path.
Overall I'm satisfied with the results. I'm also very satisfied with
the support I get when I run into problems with a design.
- Bas Stuifmeel of Philips Semiconductors
We use both Synplify Pro and Synopsys DC in the Verilog RTL-to-FPGA
Masters of Microelectronics course I lecture. We have not really
pushed the limits, but Synopsys seemed to have a lot more issues in
getting through the design flow. Synplify is nice to use, and I
recommend it for FPGA compilation to my students (except when the
FPGA libraries aren't supplied as part of the academic kit... grrr.)
- [ An Anon Engineer ]
Synplicity has worked fine for me whenever I have used it.
- [ An Anon Engineer ]
I am a Synplify Pro user since 4 years, and never really worked with
another tool for FPGA synthesis. Why? I would prefer not to teach you
why I have chosen Synplify Pro but why I am not working with others.
- Easy to use and intuitive schematic browser is the minimum requirement
when you want to do synthesis. This is not the case with Xilinx XST,
this tool has a crappy browser, not possible to follow nets, get
fan-in fan-out cones. Moreover, it is not able to understand some
standard RTL codes. At least, Synplify Pro is able to provide a
friendly graphical interface.
- Before going to Synplify Pro, we have made some comparisons between
Mentor Precision and Synplify Pro. Even if the Mentor license price
is lower than Synplicity, QoR is the inverse! We did tests onto
billion gates chips with complex clock trees and power isolation
areas. Mentor Precision tool was using some global resources such as
global clock buffers where Synplify Pro was using local routing
(saving global resources for other purposes). By the end, Mentor
Precision was using 5% more logic than Synplify, really embarrassing
when your FPGA is already 90% full.
- Finally we have taken Synplify Pro licenses. Tool is now working under
Linux environment, like others EDA, that allow us to speed up our
development run time.
We never found big issues with Synplify Pro except with clock tree.
Indeed, Synplify Pro has the bad habit to split the clock nets between
"clock used as DFF clock" and "clock used as LUT (logic data) input".
In other words, when doing clock gating with a LUT, it is hard to keep
the clock onto a dedicated clock line (Global clock buffer output) and
not routed onto simple nets (even if the clock is already present at
the SLICE input.
- Yannick Gilbert of NewLogic Technologies AG
I personnally consider that Synplify Pro is really still the best
synthesis tool for FPGAs. However, I have the following negative
comments - I mean, I would like to see some improvements :
One of the features I liked more about Synplify-Pro (some years ago)
was that I could compile my designs with no or very few options, and if
the VHDL source code was clean, the synthesis results were automatically
optimized for the selected target.
Since some months (ver 7.7 if I remember), Synplify-Pro doesn't map
anymore the flip-flops into IOBs if we do not add a constraint file.
I would like this to go back to the previous versions (there is no
reason to require a mandatory constraint file to get "normal results".)
One of the best features of Synplify-Pro is the RTL view that is much
better than the one of the competition. However, there is a big
inconvenient that appeared some years ago.
Input buffers, input FFs, output buffers, output FFs, internal Tristate,
and sometimes internal Flip-flops are drawn in the RTL view as single
instead of being grouped (I'm talking about busses). This strongly
limits the schematics readability, and in addition I see no reason for
ungrouping them.
For many years, I said (and sent design examples) that "loadable
accumulators" where not optimized with Synplify-Pro : the synthesis
results (confirmed after Xilinx MAP and PAR) show twice the number of
used SLICES, and of course, it results in a slower design. No matter
about the Xilinx familly you want to use...
Of course, sometimes there are bugs, but we can consider this normal.
I've never seen an EDA tool with no bugs.
- Edgard Garcia of Multi Video Designs
Synplicity is a good company. They came to the aid of my struggling
startup with an eval license for their Synplify ASIC synthesis tool
when I needed to get some area and timing estimates to help close a
deal that would fund the company. I will not forget the Synplicity
generosity and their understanding of the challenges of starting
a business.
Synopsys' response had been, "What can you do for us first?"
- Jonah Probell, Consultant
I used Synplify ASIC fairly intensely at my old company about a year
ago, so my comments are a bit dated. My new company has just purchased
it for our next chip, so I will have further experience later on.
We purchased Synplify ASIC because my previous experience said it can
do the whole job and we did not buy any Synopsys tools. This was done
to save money. My old company had both Synopsys and Synplify so I can
compare those two. I have no experience with Get2chip.
When I used Synplify ASIC, there were some bugs but they were very
responsive to fix them. Our design was hierarchical with the largest
blocks about 200K instances, 400K gates or so. Mixture of memory and
standard cells. Since this data is so old, I won't spend too much
time on it.
Synplify ASIC Synopsys DC
Compile time 3 hrs 24 hrs
Performance 4.1 ns 4.2 ns
Area ~same
Synopsys DC was better (MHz) for blocks with ALU's and multipliers.
Synplify ASIC was better for designs with MUXes and random logic.
We actually got best results using a 1 - 2 method:
Pass 1 use Synplify ASIC
Pass 2 use compile -incremental on Synopsys DC.
We were able to do clock gating and scan insertion correctly on
Synplify ASIC.
- Ralph Haines of Spans Logic, Inc.
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