( DAC 01 Item 41 ) --------------------------------------------- [ 7/31/01 ]
Subject: Cores (ASIC & FPGA), Core Tools, Core Websites
PARTS IS PARTS: Yea, cores go by the fancy name of 'IP' and design
re-usablity was Big News a few years back; but, as usual, the hype *far*
exaggerates the reality. Synopsys managed to sew up the small IP market
by embedding DesignWare parts into their dominant Design Compiler tool.
But, beyond that, IP has been a hodgepodge of mix-n-match parts from every
corner of the earth. And all that hoopla around 'design re-use'? Nobody
does it because it takes 3X the design time to implement. (Thanks, but
no thanks, guys!) One other odd note: in prior years lots of users had
lots to say about ARM and ARM cores. This year, out of 182 responses,
hardly anyone even mention ARM. (Hmm... What's up at ARM?)
"Synopsys/CoreSynthesis
Technology based on coreConsultant, coreBuilder tool. Tools that
generate DC/PhysOpt scripts based on constraints and design intent.
Aimed at enabling teams to push DC/PhysOpt to the maximum in hardening
cores. Tool can definitely improve timing/area results thru expert
use of DC/PhysOpt. Plan to bring it in and see how well it can be
used in helping to harden the next synthesizable core we acquire."
- [ An Anon Engineer ]
"1.1 Cores and Tools
Chipidea, SliceX and Leda Systems Inc. (not to be confused with the
French linter company that Synopsys bought) sell analog and mixed
signal IP. They will generally ship you GDSII and schematics. This is
obviously very foundry dependent and porting a block to a new foundry
is quite an undertaking.
Tensilica and ARC Cores both sell customizeable 32-bit processor cores.
Arc's claim last year was that it only takes a day to integrate it into
your system because you've customized it so well for it's environment
using their GUI. Tensilica sells an emulator board that downloads your
configuration so you can start software development early. They say
they now support multiprocessors, and have a compiler like SGI's. You
configure the core through a GUI and it spits out Synopsys constraints
and VHDL and Verilog test benches.
Infineon sells soft DSP cores. Unlimited use is $3M or $4M, limited
use less.
Retarget Compiler (retarget.com) allows you to design new DSPs using
their NML language to describe the processor. Their tool allows you to
compile and simulate programs to test out your design at a behavioral
level, then it creates RTL.
3DSP sells high performance soft DSP cores. Their software will modify
the test benches they provide to account for how you have
parametrized the core.They also provide a bus architecture if you
need multiple cores.
Derivation Systems sells a soft (VHDL) Java processor core.
TOPS systems sell heterogeneous multiprocessor soft cores. I loved
their DAC giveaway. It looked like a highlighter but was actually a
paper cutter that would cut paper but couldn't cut human skin - ideal
for children and engineers.
BOPS sells homogenous multiprocessor soft cores.
Improv sells soft cores that use Very Long Instruction Word (VLIW)
architectures. They feel that more hardware is the key to more speed,
rather than straining for ever faster clocks. The compilers for the
multiprocessors are done automatically.
eASIC sells configurable hard cores for UMC and TSMC. This sounds
like a contradiction in terms but isn't. Their cores are configured
at the via level; the layouts are such that putting in or leaving out
a few vias will alter the function.
CAST sells soft IP. All is available in VHDL and some in Verilog.
Sciworx sells VHDL and Verilog soft cores.
Telecomitalia (an Italian telecom company) sells VHDL soft cores
and C models.
Denali is selling DRAM controller IP.
Nurlogic sells DLL and PLL cores.
Synchronicity and EDAptive Computing sell tools to facilitate design
reuse. It allows for web-based archiving and cataloguing, bug tracking,
enforcing download rules, etc. People only buy one of these so these
can be mighty expensive tools. Mentor also sets up systems like this
for people, but it seems to be more of a consulting engagement than a
specific tool. I think the other tools would require some help to
set up, as well."
- John Weiland, Intrinsix
"CORES
-----
DSP Cores: 3DSP, BOPS, Infineon, Improv Systems, Lexra, QuickLogic
Didn't spend much time with these guys because it's not clear yet
that we need such a core.
3DSP
1. Older, smaller, SP3 core would has enough horsepower for
audio decode
2. They have software libraries for MPEG1, AC3, AAC, MP3 decoding.
3. In 0.18um, core is about 1.3 mm^2, plus need about 16kB ICache,
16kB DCache, 16 kB DMem. Can go to about 200MHz.
4. VHDL!!
5. They have other libraries: Filters, Transforms (FFT, DCT/IDCT),
Video (JPEG so far, future: H.263, MPEG-4); Wireless (Viterbi,
Turbo)
Infineon
1. 16-bit cores aimed at communications
Improv Systems
1. Synthesizable Verilog RTL cores
2. VLIW Architecture doesn't use register files
3. Targeted voice-coding applications (e.g., voice-over-IP & -DSL)
FPGA Cores: Adaptive Silicon
1. Provides FPGA logic core in TSMC & LSI 0.18um processes
(future: UMC)
2. Basic block: 1.5 mm^2, 1500 gates, SRAM based
3. Can comebine up to 16x of these (25 kgates, 25 mm^2)
4. Business model: n x $100k per design plus $0.02-$0.05 per basic
block royalty per chip. Ouch.
5. Seems pretty big. In a few mm^2 we can put a QMM instead."
- Henry So of Mobilygen, Inc.
"Biggest Lie? Zvi OrBach of eASIC said he can do 20-30 K gates/mm^2 of
FPGA programmable logic within his one-mask programmable core. Xilinx
and Altera are just now breaking 2 K gates/mm^2 when they do them in
full custom logic, and they do this a lot better than eASIC."
- [ An Anon Engineer ]
"eASIC claimed 60 Kgates/mm^2 at 0.13 micron, and pulled standard cell
number down from 200K to 120K for more favorable comparison. They
implement logic with SRAM-based look-up-tables. Claim 20 nW/gate/MHz
power, vs 15 for std cell and 500 for FPGA. Their number is too low
relative to std cell to be believable."
- Deepak Sherlekar of In-Chip Systems
"Three vendors providing FPGA Cores
ACTEL VariCore
- Matured FPGA vendor
- Embedded FPGA core with scalable, configurable programmable logic
blocks from 2.5K to 40KG on 0.18um technology
- Silicon-proven on TSMC, UMC, and Chartered
Adaptive Silicon MSA (Multi Scale Array)
- Embedded FPGA Core with scalable logic blocks from 1.5K to 25KG on
0.18um (4 or 5 layer metal) technology
- Performance : 50-100MHz typical system clock
eASIC : eASICore
- Composed of 2048 eCells (Look Up Table)
- Customization done by 5th and 6th metal layers (like GA)
- High density (0.9mm2 with 25KG equivalence on 0.18um : 20x against
FPGA), high performance (up to 400MHz)
IP Vendors (FPGA cores)
Comparison : FPGA, eASIC(metal customization), ASIC
- TAT : FPGA(0days) < eASIC(5-10days) < ASIC(30-60days)
- Density : ASIC(60KG/mm2) > eASIC(30KG/mm2) > FPGA(1.5KG/mm2)
- NRE : FPGA(zero) > eASIC(low) > ASIC(very high)"
- [ An Anon Engineer ]
"Intellectual Property/Design Reuse Web Sites:
There are some several organizations and companies in the IP
business. RAPID (rapid.org) is an industry organization that
promotes the use of IP and has a catalog of cores from some IP
vendors. The French company Design and Reuse (design-reuse.com)
is basically a storefront for small IP creators. They have almost
2000 cores in their catalog from everyone imaginable. In order to
differentiate themselves from the obvious alternative of simply
doing a web search, they have some tools for transferring and
controlling proprietary files. The Virtual Component Exchange in
Scotland (vcx.org) say the organizations listed above are just
aimed at connecting buyers and sellers, while they are aimed more
at the entire process, and work on standardizing sales contracts,
arbitrating disputes, etc. RAPID and VCX sort of work together.
The VSIA (Virtual Socket Interface Alliance) is an organization
that is trying to create a small number of standard busses that
everyone will use on every chip, so that you can just plug IP from
various vendors onto your standard bus and everything works together
without a hitch. The problem has been that in order to handle all
possible users, the bus structures tend to get very inefficient.
I personally think tools like YXI (or sort of like Sonics or CoWare)
that automatically synthesize interfaces to standard busses have a
better chance, but they don't seem to be taking off.
Palmchip sells you an RTL platform (a skeleton for your chip) that
you then flesh out with IP from a fixed set vendors which will plug
into the Palmchip busses - the VSIA goal. They also have common glue
logic blocks and claim you can sometimes build the whole ASIC without
ever doing any RTL coding. They also have tools to verify that your
design properly interfaces to busses.
Sonics, Inc. sells an on-chip micronetwork. It uses very wide,
unidirectional point-to-point busses that are certainly unlike
anything you would use on a board. They say that the Palmchip network
is a clever design for computing but is not for real time data and
also is not scalable like theirs. They say theirs decouples the IP
from the network (for example, your cores change clock rate
independently). They also say that Palmchip is both idiot-proof and
genius-proof. They give you lots freedom to meet your specific needs
(or is it rope to hang yourself?)"
- John Weiland, Intrinsix
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