( DAC 01 Item 27 ) --------------------------------------------- [ 7/31/01 ]

Subject: Synopsys PhysOpt vs. Cadence PKS

WHERE'S WALDO?  When I was compiling this report (cutting and pasting all
those many user responses), on the 30th user letter, I stopped to see what
I had so far.  I was surprised.  In those 29 user responses I had already
found 18 comments on PhysOpt but only 2 references to Cadence PKS?!  Huh?

I looked and found all sorts of user comments on Cadence Assura, Cadence
NC-Verilog, Cadence Silicon Ensemble, Cadence Testbuilder, Cadence NC-SIM,
Cadence Dracula, Cadence Signalscan, Cadence Verification Cockpit, Cadence
Ambit BuildGates, Cadence Formal Check, Cadence Quickturn, Cadence
Integration Ensemble, Cadence IC Craftsman, Cadence Qplace, Cadence Warp
Route, Cadence Virtuoso, Cadence Opus.  I had no shortage of Cadence user
comments -- I was just seeing a dearth of user comments on PKS!  Huh?  But
what about Ray's quarterly conference calls?

  "It's one thing for a customer to buy a few evaluation copies to see
   how our product might work.  It's quite another to buy a product in
   volume and to see proliferation of that product."

        - Ray Bingham, Cadence CEO, Q3'00 conference call Oct 17, 2000

  "We now have almost 50 customers who have bought PKS or SE-PKS,
   14 repeat orders, and hundreds of seats in the marketplace.  That's
   what we call the beginning of proliferation."

        - Ray Bingham, Cadence CEO, Q4'00 conference call Jan 23, 2001

I figured now was a good time to do a Missing Elf Analysis on PKS.  (This is
where you look at the environmental impact of a tool to see how widely it's
really being used.  I developed this technique 2 years ago when a Synopsys
Vera Marketing VP put out a press release claiming he had 5,000 Vera users.
He didn't.  I discovered, by Missing Elf, that he actually had only around
500 Vera users, not the 5,000 he was claiming!)

I went to www.hotjobs.com and did a keyword search for "Cadence".  I found
278 jobs.  I added "PKS" and only found 2 Apps Engineer jobs at Cadence,
Inc. -- and no user jobs.  I do the same thing with "Synopsys" to find 761
jobs.  "Physical Compiler" finds 8 user company jobs after I remove the
Synopsys, Inc. jobs.  I do the same on www.monster.com to find 305 "Cadence"
jobs, and this time, 1 PKS user job at a NY consulting co. named "Manhattan
Routing, Inc."  (Clever name.)  A "Synopsys" search turns up 196 jobs and
9 user "Physical Compiler" jobs.

OK, so if PKS and SE-PKS are "proliferating" as Ray says, I should be seeing
companies hiring people for those tools.  Instead I'm seeing people getting
hired to use PhysOpt.  Hmmm...

Oops.  Ray said "SE-PKS", too.  I go back and try "SE-PKS" and "SEPKS".  No
change.  Just that one PKS job at "Manhattan Routing, Inc." and that's it.

Now let's go check out PKS on comp.cad.cadence on www.deja.com archives.
I set the search for June, 2000 to June, 2001 and search for the word "the".
It comes back with 1,250 posts -- that's how many posts have been on the
comp.cad.cadence newsgroup for the past 12 months.  Search "PKS".  Removing
the CFP notices, I find 4 posts on "PKS" out of 1,250 posts.  Huh?!  I try
"SE-PKS" and find 0 posts; not even a CFP!  Again, I'm just not seeing this
"proliferation" thing that Ray keeps talking about.

Since a lot of Synopsys discussion happens in ESNUG, I decided to compare
these comp.cad.cadence results with "PKS" & "PhysOpt" in ESNUG for the past
year.  Using 'grep' and 'wc' on ESNUG posts 355 to 375 (the last 12 month's
posts), I found 515 people had written into ESNUG during that time.  And
the first question a skeptical reader should ask here is "But, John, are
Cadence tools discussed in ESNUG?"  Here's the 'Cadence' histogram:

   ESNUG 355   ######## 16
               ### 6
               #### 7
               ####### 13
               ############ 24 lines containing "Cadence"
   ESNUG 360   ##### 9
               ###### 11
               ## 3
               ###### 12
               ## 4
   ESNUG 365   ######### 18
               ##### 9
               # 1
               ### 5
               #### 7
   ESNUG 370   ############## 28
               ### 6
               ######### 18
               ############# 25
               ########## 20
   ESNUG 375   ### 5

Confirmed what I already knew: Cadence tools are *frequently* discussed by
users in ESNUG.  (As a sidebar, I've been privately chewed out more than
once by Synopsys senior management for allowing non-Synopsys discussion in
ESNUG.  My pushback has always been "If my users are using it, we discuss
it."  I'm *proud* to be able to say "name that tool" and be able to show you
in ESNUG what the customers using it are experiencing.  Enough said.)

Anyway, here's the histogram of ESNUG posts containing "PKS":

   ESNUG 355   0
               0
               0
               # 2
               0
   ESNUG 360   ### 6
               ########################### 54 lines containing "PKS"
               ##### 10
               ### 6
               0
   ESNUG 365   ######## 15
               #### 8
               0
               0
               0
   ESNUG 370   0
               0
               0
               0
               #### 8
   ESNUG 375   0

Believe it or not, there's *more* customer discussion of PKS in ESNUG than
there is on the comp.cad.cadence newsgroup!!!  That spike around ESNUG 361
is because Thad McKracken of Geocast wrote the first PKS tape-out story.
(FYI - Three months later, Geocast went out of business, so I don't think
his chip ever went into production, but it's a tape-out nonetheless.)  In
ESNUG 365 #2, Jay McDougal of Agilent wrote about runtime issues with PKS.
After that, user discussion of PKS *everywhere* -- either on ESNUG or on
comp.cad.cadence -- completely dried up.

(That last blip in ESNUG 374 of 8 mentions of PKS are the Magma tape-out
count -- it's users saying how they hate PKS/PhysOpt and just luuuv Magma.
I don't count that as PKS nuts and bolts usage talk.)

Now here's the histogram for "PhysOpt":

   ESNUG 355   0
               0
               0
               ######################### 49 lines contain "PhysOpt"
               0
   ESNUG 360   ######## 16
               ##### 9
               ##################### 42
               ###### 12
               #### 7
   ESNUG 365   ######## 16
               ############### 30
               #### 8
               ##### 10
               # 1
   ESNUG 370   ################# 37
               ############ 23
               ############### 30
               ######## 16
               ########## 19
   ESNUG 375   0

No mention of PhysOpt until ESNUG 358 #3, when Ken Merryman of UniSys wrote
about his IBM ASIC PhysOpt tape-out.  After that, the ESNUG PhysOpt chatter
has gone on steadily with talk about bugs, gripes, workarounds -- the usual
banter of a tool actually being used by designers to make chips.
  
And finally now, let's look at the customer tape-outs using these tools:

         Synopsys  ########################################### 170 tape-outs
      Cadence PKS  ### 12
  Cadence non-PKS  ###### 23 
            Magma  #### 13
         Monterey  0

The 170 Synopsys number comes from Aart.  In SNUG'01 #7, my readers said
they pretty much believe Aart on this.  The 12 PKS tape-outs I got from
Rashmi Murthy, Cadence Lead Applications Engineer during HDLCon'01.  The
extra 23 Cadence non-PKS tape-outs came from Ray Bingham at DATE 2001 when
he claimed "35 SPR tape-outs".  (35 SPR - 12 PKS = 23 non-PKS)  The Magma
13, I counted myself in ESNUG 374 #7.

So, from this analysis, I'm seeing only 1 non-Cadence company (a consulting
house) with one PKS job, 12 PKS tape-outs, and hardly any PKS user
discussion *anywhere*.  With PhysOpt, I'm seeing 17 non-Synopsys job offers,
170 tape-outs, and boatloads of PhysOpt user banter.  Hmmmm...

Now I know why Ray Bingham has quarterly conference *phone* calls.  He's
hiding one awful big ear-to-ear grin on his face when he intentionally uses
the words 'proliferation', 'PKS', and 'SE-PKS' together in the call.


P.S. Don't get me wrong here.  When Ray finally gets PKS working, how much
he'll make in the physical synthesis market will depend on how much mind
share and market share Synopsys has snapped up before then.  Notice that I'm
not saying "if", but "when" here.  Ray's people are not idiots.  They will
get PKS working.  They just don't have PKS working now and Synopsys is
currently eating their lunch because of it.  (But I do question what paying
$260 million for Ambit got Cadence -- if Ambit was truely worth that much,
Cadence would have been the one owning this market now, not Synopsys.)


    "Cadence Design Systems:

     I attended their "private suite" demo for the Ambit-PKS RTL-to-placed-
     gates synthesis tool, competing with Synopsys' PhysOpt.

      - supports "datapath" and "low-power" synthesis which are extra
        add-ons to Synopsys' tool
      - "datapath synthesis": automatically infers datapath vs. control
        logic, performs operator merging, architecture selection (a
        DesignWare-style library, though I'm not confident how many choices
        they give).
      - "low-power synthesis": automatic clock-gating and gate-level power
        opt. using toggle information from simulation (can't just use
        statistical estimate--must use simulation).
      - does scan-insertion/reordering
      - clock-tree synthesis (but no "useful skew" yet).
      - supposed to be large capacity; 64-bit OS port just released
      - Solaris, but no Linux support (not even close at this point)

     Silicon Ensemble adds Extraction, Route, Signal Integrity analysis."

          - Kris Monsen of Mobilygen Corp.


    "I work in the TI ASIC group, 100% of our customer base in DC-based.
     Internally, we use PKS as one of many timing closure flows, since TI
     is just so large.  CDN offers a better analog environment for our
     mixed-signal guys, who simply have to stay with Cadence."

          - [ An Anon TI ASIC Engineer ]


    "Synopsys PhysOpt?

     Good product, widely used, good documentation.  Poor correlation with
     final/detailed route, but they are working on it.  Will they get it
     right?  How long will it take to get it right?

     Cadence PKS?

     Good product, not used widely, mediocre docs.  Great correlation with
     final/detailed SE route (congestion and timing), integrated CTS,
     integrated global route.  Lots of low level control.  Great
     interactive/debug responsiveness.  PKS run times longer than PhysOpt.

     Monterey Dolphin?

     Tried it 1.5 yrs ago.  Lots of trouble getting a test case finished.
     No better results than IPO/ECO on test case.  Gave up.

     Synopsys is winning here because of PhysOpt's derivation from their
     industry standard Design Compiler.  Also, they talk about/promise to
     deliver solutions for areas where they are not so good (CTS,
     global/detailed route, congestion correlation, etc.)"

          - [ An Anon Engineer ]


    "We're using PKS for the first (official) time right now.  It looks
     good early on, with no major red-flags, yet."

          - Mike Bly of World Wide Packets


    "Mentor has no suite solution.

     Avanti lacks a synthesis or RTL-planning capability.

     Ambit PKS has not been updated in 3 years.

     All the separate frontend/backend players are looking outdated, even
     Synopsys, notwithstanding Route66."

          - [ An Anon Engineer ]


    "We have tried PhysOpt in the past.  But with PKS integrated closely
     into Silicon Ensemble, we really don't need the Synopsys tool."

          - Andrew MacCormack, Cadence/Tality


    "PKS - the world's longest beta eval."

          - [ An Anon Engineer ]


    "Cadence PBOPT is limited to only buffering and sizing and relies on
     elmore delay calculation.  A fairly basic tool which should be
     obsoleted by PKS if they can ever get it to work."

          - from "Been There, Done That" in ESNUG 374 #7


    "One of our teams has been very successful with BuildGates/PKS.  The
     rest of our teams use DC/PhysOpt.  Both PKS and PhysOpt have helped us
     meet timing.  We anticipate even more use of these tools, especially
     PhysOpt since as we are a design center we need to be able to use the
     constraints that our customers provide.  Most of our customers use 
     DC for initial synthesis, so we need to use PhysOpt for physical
     synthesis -- at least until we get closer to RTL handoff, which still
     seems far away."

          - [ An Anon Engineer ]


    "DC has a big runtime advantage over Ambit-RTL and a small QOR
     improvement.  Ambit needs the PKS stuff to have an advantage over
     Synopsys's tools, but PKS always seems to be an extension of Silcon
     Ensemble, rather than an extension of Ambit."

          - [ An Anon Engineer ]


    "Route66 finally gives Synopsys a complete solution from RTL to GDSII to
     compete with the Cadence PKS tool set.  The CadMos integration into
     Cadence will be a closely watched one.  It greatly strengthens Cadence
     position in the noise analysis arena.  If the PKS marriage with CadMos
     is successful, then PKS definitely holds some advantage in the physical
     synthesis arena.  Right now there is only some level of integration
     between CadMos tools and PKS."

          - [ An Anon Engineer ]


    "I also attended the Synopsys PhysOpt & Clock Tree Compiler demo:

      - New capabilities planned for end-2001: RTL-to-placed gates with
        minimal physical constraints (i.e., without needing a floorplan),
        for early feedback on synthesis quality while avoiding wireload
        models.

      - Clock Tree Compiler:

        - doesn't support useful skew (yet)
        - works along with placement

      - They're proposing the use of "Interface Logic Models" to improve
        capacity: bascially a black-box model but with the real logic 
        between the block's pins and first rank of internal flops (take a
        block and "suck out its guts").

      - 64-bit Solaris support end-2001

      - Linux by end-2001?

     Not much new in the RTL-to-Gates Synthesis area."

          - Kris Monsen of Mobilygen Corp.


    "PhysOpt (Physical Compiler):

     They're planning for the upcoming PhysOpt 2001.08 to be able to
     compile RTL-to-Placed-Gates (RTL2PG) w/ minimal physical constraints.
     Your detailed floorplan will be replaced w/ a script of size, aspect
     ratio and pin locations.  This is to address the capacity issues with
     RTL2PG, allowing bottom up compiles while eliminating wireload models.
     This should give a better starting point for gates to placed gates
     (G2PG) optimization.  A Linux version will also be available.

     Possible (but not promised) enhancements in PC2001.08:

          - Via resistance included in delay estimate
          - Buffering along detour nets
          - Rectilinear macro support
          - Wide wire support
          - dont_move_size_only
          - ECO change list reporting
          - Legalization improvements for n-row high cells
          - Post route scaling factor for back annotated RCs

      GUI improvements (possible):

          - improved load time (update_timing turned off)
          - display illegally placed cells
          - display sites in floorplan
          - object selection by name
          - scan chain visualization

     They also spoke of PhysOpt using of multiple CPUs for placement.  I
     suspect these promised enhancements will definitely be in the next
     release of PhysOpt if they don't appear in August's 01.08 release."

          - Bob Wiegand of NxtWave Communications


    "In general we are pleased with the evolving PhysOpt.  We still have a
     need to handle ECO's and metal only changes.  In the last five ASICs we
     produced, we used ECO Compiler once.  With the such low usage it is
     difficult to maintain expertise in the tool and difficult for the
     vendor to make money on the software.  

     My impression of Cadence PKS is that it has a lack of support.  Last
     March I requested Cadence to come in and give us a demo.  They never
     got back to us.  The same thing happened the last two times we wanted
     to look at PKS.  Support is important to us and we have had very good
     support with PhysOpt."

          - Ken Merryman, UniSys


    "I'm very concerned by the reports of Magma BlastFusion not being able
     to handle large designs, but that is also what I've discovered with
     Cadence PKS.  In Cadence's case, we evaluated PKS last year, and don't
     like the product.  It is a wrapper built around a bunch of tools which
     don't work well and don't give us the hooks to make necessary
     adjustments (which were available with the standard SE product-line).
     The entire PKS flow is worrysome, since Cadence did not upgrade their
     floorplanning capabilities to handle anthing larger than a 200 K
     standard cell design.

     I don't like Monterey Dolphin for many of the same reasons.  In talking
     to their sales and tech reps, we're supposed to set everything up
     front, hand it off to Dolphin, and come back a couple of days (or a
     week) later to examine our completed design.  I'm never going to give
     anyone that kind of leeway.  I need to be able to look at things at
     each step to determine if I need to tweak the layout/floorplan, or send
     it back to the designer.

     I like Avanti's Saturn features, and look forward to using Jupiter in
     the future, but since Jupiter uses Design Compiler for it's synthesis,
     but w/o the DesignWare package, they will always be behind the curve.

     Synopys PhysOpt is the real winner here.  The tool is easy to use for
     anyone with DC experience, and they make a real effort to link into
     both Cadence and Avanti tools for clock placement and routing."

          - [ An Anon Engineer ]


    "We've been happy with Synopsys PhysOpt/Physical Compiler.  Had trouble
     during the first few months because we had to write our own code to
     import pre-existing power routes and top-level blockages from our
     floorplanning tool into PhysOpt.  I would guess that the data
     translation for PKS in and out of Cadence floorplanning/P&R tools is
     smoother, and the core algorithms have probably become equivalent, but
     PhysOpt does have the advantage of running quite well on Linux."

          - [ An Anon Engineer ]


    "I trust PhysOpt more due to the higher degree of success in the
     customer base.  The Magma/Monterey/Cadence PKS presentations were
     great, but they could be lies all lies."

          - Phil Kuglin, Credence Systems Corp.


    "PhysOpt rocks.  I love the way the whole flow in now integrated within
     Synopsys.  Mind you, what Synopsys is promoting in PhysOpt is not
     always true.  I've seen problems with their so called integrated flow
     with scan order.  It doesn't work if you don't put an attribute on the
     db file to tell PhysOpt that the design is test ready.  I believe a
     STAR has been filed for this.  If you read in a netlist which has
     existing scan, PhysOpt reordering produces a zillion "assign"
     statements even after setting "physopt_fix_multiple_port_nets true"
     (a hidden variable!)  WHY is it hidden?  Secondly, why is it there at
     all? -- especially since we already have to contend with
     compile_fix_multple_port_nets.  There are also problems with PhysOpt
     when the design is severly underutilized.  You get a clumping effect.
     You have to play with numbers of yet another variable to fix the
     clumping effect.

     Even with all these issues, PhysOpt is the way to go.  You do save a
     lot of time with PhysOpt freeing you from fighting the backend tools.
     In addition, the result produced by PhysOpt is much more superior to
     Avanti's tools."

          - Himanshu Bhatnagar of Conexant


    "I used PhysOpt to tapeout our 500 MHz SV1e processor.  The tool wasn't
     perfect, but at least it was similar enough to Design Compiler that the
     learning curve wasn't steep.  I'm sure that many improvements have been
     made since I used it last.  I spent zero effort with their GUI and with
     their PrimeTime.  I used the IBM toolset for place&route and static
     timing analysis.

     There's only one secret to solving hierarchical physical design issues:
     design hierarchically.  It simplifies compilation, test insertion,
     clock insertion, and formal verification.  Other than that, it's just
     a good idea. We were able to work with IBM to find the appropriate
     level of hierarchy which met their needs (from a tool perspective) and
     our needs.  We knew the requirements before we synthesized, and we
     designed to exploit the hierarchy."

          - Roger Bethard, Cray Computers


    "We haven't investigated a lot of these other tools for four reasons: 

      1.) First and foremost Synopsys PhysOpt is working well for us.  
      2.) We have very limited budgets.
      3.) It takes a lot of time to evaluate a tool we are going to
          spend 100k++ on.
      4.) using IBM fab locks you into their toolset somewhat since you have
          to sign off with it.

     You can use other toolsets but it's extra work.  (I'm not saying this
     is necessarily a bad thing, just a fact of life.)"

          - Christopher Gorzek, Cray Computers


    "Synopsys PhysOpt is the one to beat in physical synthesis.  But
     interestingly, the related Route Compiler looks like an also-ran
     product.  Synopsys definitely still has some work to do to step
     beyond placement."

          - Mike Carter of Mosaid Technologies


    "I like what Synopsys is doing.  We have been using PhysOpt for a while
     now with decent results and Synopsys is incrementally improving the
     tool with each release.  PhysOpt is not perfect yet, but definitely
     moving in the right direction.  With Route66 and Clock Compiler, it's
     moving more in the direction of a complete tool.  I guess that you
     could say that I am a fan of evolution over revolution.  :-)"

          - Lars Bo Graversen, MIPS Denmark


    "For now, Synopsys PhysOpt has the lead."

          - Bill Cox of VI ASIC


    "I have had good luck using PhysOpt in my design.  Timing closure looks
     really good.  The biggest conceptual problem is that it takes more time
     in PhysOpt than you did in DC.  Most of this is because you pull a good
     portion of the "pain of the backend" into the synthesis/optimization
     stage.  There are still some holes in the flow, but Synopsys has seemed
     to fill those rather quickly.  I'm encouraged by the announcement of
     the CTS and router features being added. 

     Also, although I have not yet tried this, you can incorporate the
     advantages of Module Compiler with PhysOpt and purportedly gain
     optimizations in placement from the embedded knowledge of Module
     Compiler.  I will be trying this soon.  For datapath, once it works
     well this will be a significant enhancement."

          - Dave Brier, Texas Instruments


    "With their announcements of Route Compiler and Clock Tree Compiler,
     Synopsys is poised to dominate the industry by converging logical and
     physical design.  Whether or not they are successful, remains to be
     seen.  However, I believe that design teams that are dependent on
     Module Compiler (like us), will become more and more dependent on
     Synopsys for logical & physical design tools.  I think it's almost
     inevitable that we'll need to get Physical Compiler (PhysOpt) at some
     point, and then in the future, it's not a big leap to imagine us using
     Route Compiler, Clock Tree Compiler, DFT Compiler, Power Compiler,
     SystemC Compiler, etc.  We'll see.

     But for us to switch to anyone's physical synthesis, we need a total
     solution.  Having something that kind of works but I have to give up
     BIST or some other critical part of my design flow just does not work.
     It has promise and I like to solve the problems in DSM but a 90%
     solution just does not cut it."

          - Phil Hoppes, Intersil


    "We've had good results from Synopsys PhysOpt."

          - Michael Hede, MindSpeed


    "Synopsys PhysOpt seems a lot easier to implement, as it requires a
     designer to add a couple of lines to his DC script and is closely tied
     with DesignWare models.  It would not make sense to use PKS with
     Synopsys DC.  It would be suicidal to switch to Ambit in the middle or
     start of a new project as it involves new learning curve."

          - [ An Anon Engineer ]


    "My basic design philosophy is not to count on anyone's physical
     synthesis to get my design through tape-out.  I'm hoping that by the
     time I really need it the technology is proven."

          - [ An Anon Engineer ]


    "The big eye-opener for me is that PhysOpt can be used as a synth-aware
     placement tool as well as a placement-aware synth tool.  This means the
     current model will continue to work for a while.

     Using PhysOpt in RTL-to-placed-gates mode raises interesting business
     questions.  For non-COT shops, who will own and run the tool?  While
     RTL sign-off is appealing to management, I can't picture surrendering
     control of half (or more) of the chip schedule to an outside party."

          - Paul Zimmer of Cisco Systems


    "We are still developing our new Synopsys PhysOpt flow but the folks
     doing it are enthusiastic.  I think Synopsys remains king for us here."

          - Tom Coonan, Scientific Atlanta


    "Physical Compiler (PhysOpt):

     PhysOpt is the physically aware synthesizer from Synopsys.  It was
     defined as a superset of Design Compiler.  The demo detailed two
     different flows: a RTL-2-Placed-Gates and Gates-2-Placed-Gates.

     Key features:

     * PhysOpt uses actual interconnect information instead of custom
       wireloads.  This makes the synthesis far more efficient. 
     * the RTL-2-Placed-Gates flow does not require a floorplan.  The RTL
       modules are synthesized into structural netlists using PhysOpt.  The
       floorplan is required only after all the modules in the super block
       are synthesized.
     * fully integrated with DFT Compiler.
     * integrated with Power Compiler.
     * post place optimization capabilities. 

     Clock Tree Compiler:

     * Creates clock trees for high fanout nets.  It is fully integrated
       with PhysOpt.  Useful clock skew features will be introduced later
       this year.  The clock tree compiler uses buffers and inverters.  It
       supports gated clock tree synthesis as well. 

     Finally, I was struck by the simplicity of the Synopsys demos.  By
     comparison, Astro looked far too complicated.  Astro also has a lot of
     user options and settings that can sometimes cause confusion.  Synopsys
     probably hides these options from the users.  The GUI in PhysOpt and
     Route66 look pretty basic.  Some of the charts in the PhysOpt demo made
     the Design Compiler timing look pretty bad, which begs the question: If
     PhysOpt were so good, why would we need DC in the flow?  (unless is is
     a poor man's option to PhysOpt.)

     I also talked to Sequence design and Simplex.  Did not have a chance to
     see their demos.  Simplex's X-architecture is under tight wraps and
     only shown to very large customers with NDAs."

          - [ An Anon Engineer ]


    "I've heard of several companies using PhysOpt in production and
     believe it's valuable.  I want to get rid of WLMs and timing closure
     iterations.  I wish LSI Logic + more ASIC vendors supported PhysOpt!"

          - John Busco of Brocade


    "Synopsys PhysOpt is the real competition here."

          - Dan Clein, PMC-Sierra


    "We are more focused on DSM effects (IR Drop, Cross-talk), and timing
     convergence.  So we put all our hopes in Astro and PhysOpt."

          - [ An Anon Engineer ]


    "PhysOpt still looks pretty damn good.  It may get a lot of synthesis
     guys into the placement world."

          - John Szetela of AMD


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)