( DAC 01 Item 25 ) --------------------------------------------- [ 7/31/01 ]
Subject: Design Compiler, Ambit-RTL, Get2chips.com, Synplicity, Incentia
FOUR MORE "ME, TOO" TOOLS: Yawn. So you're telling me there's now 4 more
EDA companies trying to snatch the ASIC synthesis market from DC? (I'm
sorry for yawning, it's just that I've seen this story so many times
before...) What I've seen each time is that too many chip designers have
too much experience, scripts, and know-how invested in Design Compiler. And
they rather not risk their chips (or their careers) on a new RTL synthesis
tool. Even the managers at LSI are afraid to do designs relying solely on
Ambit -- and LSI was a big backer of Ambit before it was aquired by Cadence!
Get2chips, Synplicity, Incentia, and Ambit all have the same flaw: they're
"me, too" tools. The best they can do is to catch up with DC -- they're
just re-solving an EDA problem that's already fully solved. PhysOpt, PKS,
and Magma are where the real battle is being fought these days.
"Ambit got Synopsys to improve Design Compiler, and maybe get2chip will
do the same. That's a good thing, because most people use Design
Compiler. I don't think any tool can replace Design Compiler as the
"industry standard" until the next paradigm shift.
Behavioral Compiler started as a nice idea, but never became "the next
paradigm shift", and other companies that try to build a better
Behavioral Compiler are wasting their time."
- Oren Rubinstein of Nvidia
"I personally have done several benchmarks of Ambit vs DC. Ambit has
come out the DEFINITE winner each time. However, we have too much
invested in Synopsys DC to change -- even with a price incentive.
Management is too leery of switching to a new synthesis tool. Granted
they are all in favor of it, but don't want it to happen on their
project. Too bad."
- Duncan Halstead, LSI Logic
"My boss keeps threatening to switch us from DC to Ambit because it's so
much cheaper. But every design project has such an aggressive schedule
that we always end up using DC because it's a low schedule risk."
- John Lynch of Pixelworks
"We have seen poor results from Ambit when compared to DC."
- [ An Anon Engineer ]
"I hate everything Synopsys. I would love to see Cadence Ambit get
more market share."
- Tom Loftus, Intrinsix
"Quite happy with DC. Evaluated DC vs. Ambit and got quite similar
results. Thinking about switching -- not enough resources to complete
the evaluation for the whole flow. Do not use behavioral synthesis."
- [ An Anon Engineer ]
"Synopsys Design Compiler continues to be the synthesis tool to beat.
I think Cadence-Ambit will shortly follow the Cadence-Synergy
synthesis tool to the grave. I think Cadence shot and continues to
shoot itself in the foot by not working with recognized consultants
for fear of losing training and consulting revenue. This past year,
I had a customer request Verilog for synthesis training using
Cadence-Ambit tools. I asked their local Cadence reps for access
to software and temporary licenses to prep the labs to accommodate
Ambit tools. The Cadence rep declined, citing the fact that Cadence
had their own training that they could offer. I told the client I
could not do the training unless they would permit me to do the
training with Synopsys synthesis and ModelSim Verilog simulation.
The customer, tired of Cadence sales games, had me do the training
with Synopsys & ModelSim. This is not the first Cadence customer
to receive such Verilog training.
The Get2Chip presentation was impressive. I am impressed with their
existing Verilog-synthesis capabilities and their ability to support
Superlog designs. David Knapp (author of the Behavioral Compiler
book) has his team doing what appears to be impressive synthesis.
This might be the first company to give Synopsys competition since
before Ambit was acquired by Cadence."
- Cliff Cummings of Sunburst Designs
"We continue to be forced to use dc_shell via the good efforts of a
third party and have not taken silicon to fab using Ambit BuildGates.
But we continue to be a fan of Ambit BuildGates for its speed and the
quality of the pre-layout netlist that we use for gate-level sims while
waiting for a netlist from dc_shell."
- David Hollinbeck, LTX
"We trust Design Compiler. We tried Ambit back in the beginning and
could seem to get support then. I have heard things have changed
especially with PKS, but why change if it's not broke? Our next set
of designs (next year) are moving to 0.13 u so we will relook then."
- Phil Kuglin, Credence Systems Corp.
"SmartSand:
They sell a tool for idiot-proof synthesis that takes your top level
constraints and automatically does the scripting for Synopsys or
Cadence's Ambit. It sounds an awful lot like the Automated Chip
Synthesis that comes free with Synopsys Design Compiler now - not sure
why a Synopsys user would buy it. Ambit might be another story. They
also have something for IP providers to send encrypted constraint
information along with their core."
- John Weiland, Intrinsix
"Synplify ASIC and Incentia -- I thought they were low end tools so
I didn't take them seriously."
- Phil Kuglin, Credence Systems Corp.
"Synplify ASIC looks very good, if their claims are true. Results
matching those of Ambit and DC, but from 4x to 20x faster. That means
a whole lot larger designs can be synthesised in a one-er, eliminating
the tedious timing budgeting and bottom-up compiles that we need now.
Also it's much easier to use. Ambit's problem in gaining market share
from DC was that people had a huge investment in DC scripts that they
would need to convert to Ambit ac_shell."
- [ An Anon Engineer ]
"Synplicity's Synplify ASIC: The tool is VERY fast. From scratch it
maps a design much faster than Design Compiler. Once Synplify has
compiled initially, design changes are blindingly fast. The tool
has no problems importing Liberty libraries and macros. The beta
version was quite buggy, but I assume that it is fixed by now. They
claim to use the same SDC as Synopsys, but this is not the case.
That's too bad for legacy design or for using the same scripts for
synthesis and static timing. Reportedly, Synplify will be able to
output an SDC readable by PrimeTime. They have the equivalent of
compile -scan but not insert_scan."
- Kristie Armentrout of Tektronix
"I was impressed by the Synplify-ASIC presentation. If they can meet
their claims of 10-15x runtime improvement with improved quality, we
would like to know that. However, we need to be compatible with our
customers, and today, that means Synopsys Design Compiler. A near
term purchase is highly unlikely."
- [ An Anon Engineer ]
"I was particularly impressed with the Synplicity Synplify partitioner;
drag and drop partitioning, now that is definitely some slick code!"
- Tom Moxon of Moxon Design
"Synplicity SynplifyASIC: New, just announced ASIC synthesis tool.
Looks to be a simple to run as their FPGA tool. Claims to be high
capacity and very fast. Imports and outputs in db format.
Has an HDL reader that lets you cross probe RTL and gates.
The timing engine looks like it is very integrated and
allows for top-level constraining that filters down to the
lower blocks. No need to time budget. Brand new, not shiping yet."
- Peet James, Qualis Design
"Saw the demo on Incentia before going to DAC. Kind of like it. But
not many people went to their DAC booth. Wonder how many people
actually use it."
- [ An Anon Engineer ]
"Incentia works OK, has timing-driven placement capability and claims
better QoR/faster runtimes at a fraction of the Synopsys list price.
Synopsys ACS is extremely powerful, though it is relatively immature.
ACS Strengths
- autoconstraint budgeting is an enormous productivity boost
- ability to launch multiple parallel jobs
Weaknesses
- you will probably have to tweak partitioning manually on large
designs, running several experimental runs before finding the
best. Can set a max- but not a min-percentage unmapped gate
area threshold. (Min-percentage would be equally useful?)
- toplevel script must be manually edited
- mixing Tcl and dcsh scripts and constraints is a pain; move to Tcl"
- [ An Anon Engineer ]
"Incentia is a new entrant in the field who is in direct competition
with Synopsys Physical Compiler. It takes either RTL or a netlist and
produces placed gates. They say their customers are just now
starting to get tapeouts. They say their customers are shy about
being identified for fear Synopsys will wreak terrible revenge upon
them - hmmm."
- John Weiland, Intrinsix
"I'll definitely stick to DC/PhysOpt, unless I hear good comments from
Incentia/Synplicity in ESNUG."
- [ An Anon Engineer ]
"Actually, we are evaluating Get2Chip. Works pretty well out of the
chute. Seems to be a clean, well-architected product. Juicy news:
it synthesizes our design faster (by about 3x) top-down than Synopsys
does top-down and achieves the same or better results. HOWEVER, we're
still able to squeeze more out of our bottom-up Synopsys flow. So the
jury's still out whether we'll switch. Get2Chip is very responsive
and interested in improving their product -- as a small company we get
a LOT more attention from their R&D/AE guys than we ever would from
Synopsys. They're "hungry" -- I like that. This is very early the
evaluation cycle, though. I'll send out more results later."
- [ An Anon Engineer ]
"Synopsys has the best presence, Get2Chip looks very very interesting
however. I've spoken to people at Cisco who have seen dramatic
improvements over DC (runtime and QoR). I'm hoping that Get2Chip will
force SNPS to innovate even more with their baseline synthesis/timing
algorithms, which will ultimately help the industry.
CDN Ambit is a good tool as well - but lacks market presence, and lacks
the technical buzz that G2C has received."
- [ An Anon Engineer ]
"Get2Chip: new architectural & RTL synthesis tool (Volare),
-------- and Topology-driven synthesis (Topomo)
1. Volare looks like a promising alternative to Synopsys' Design
Compiler tool.
2. Main advertised feature: huge capacity; it is supposed to be
able to synthesize a million or more gates all at once, top-down,
very quickly, and get better results than customer's Synopsys-based
bottom-up flows. They have done one 2.5 Mgate chip in 12 hours.
Their advertised target is 10-20 Mgates.
3. Have a DesignWare-like library of arithmetic components w/multiple
implementations, and does operator merging with CSA trees.
4. Tech. mapping algorithm makes good use of wide-fanin gates (4:1,
8:1 MUXes, big AOI/OAIs, wide NANDs, etc.).
5. Topomo tool performs physical grouping and partitioning of the large
design into small (2,000 - 50,000 gates, user-defined) clusters,
simultaneously placing the clusters and extracting routing info;
this physical placement & long-wire routing info. is:
- fed back into the Volare synthesis tool, for more accurate
wire delay
- and fed forward into any block placement tool (via a PDEF file)
that will perform the detailed placement (& routing) of cells
within the physical clusters.
6. Linux or Solaris (they develop under Linux!)
7. Also reads Superlog."
- Kris Monsen of Mobilygen Corp.
"Get2Chips: Topomo
- Essentially, equivalent to ChipArchitect + Physical Compiler
- Invokes Volare, their synthesis tool
- Creates interface to Apollo(Avanti), Tera-Place (Mentor)
- Successfully tested using 2M gate design running @ 400Hz (0.18u)"
- [ An Anon Engineer ]
"Get2chip
Volare is an "architectural synthesis" tool, (read "Behavioral Compiler
clone, but hopefully not as much of a dog") yet another in the herd of
tools claiming to move design to a higher level of abstraction. It
takes architectural/behavioral Verilog or Superlog as an input and
outputs an optimized Verilog netlist and behavioral RTL for simulation
(the behavioral RTL generation is akin to what Module Compiler does for
simulation, but this tool claims to handle both datapath synthesis and
control RTL). Because the Verilog is autogenerated, there is no way to
do final equivalency checking on ECO'd gate-level netlists vs. the
source code. We were a little bit afraid of this tool, because the guy
doing the demo said things like, "Oh, it infers state machines and
eliminates manual coding of the states." We also don't trust the
performance of Verilog generated from behavioral descriptions. Not
yet. Volare also does Synopsys-like resource sharing and
Module-Compiler-like automatic pipelining. They have a library of
useful parts (different adders, etc), like MC, but not as big of one.
They are working on a manifestion of Power Compiler."
- [ An Anon Engineer ]
"Most interesting is Volaire from Get2Chip since it reads Superlog."
- Anders Nordstrom of Nortel
"I've heard from friends that get2chip has something to look at and that
Synplicity has a decent ASIC tool. But we're using Synopsys tools for
synthesis unless there's an extremely good reason to switch (like
Synopsys goes out of business.)"
- [ An Anon Engineer ]
"Design Compiler is still the champ. After using it for years, I
really don't have any complaints. I definitely don't want to debug
a new ASIC synthesis tool. I remember DC 1.x too well.
Still haven't seen anything in the Behavioral Compiler world to make
me see any need for such a tool. My take is that BC works great for
1% of the designs but is a nightmare for the other 99%."
- Rick Price of Ensemble
"The code out of Behavioral Compiler works great in Synplicity for
FPGAs."
- [ Kenny, from South Park ]
"Some designers here have used Behavioral Compiler, and are glad with
it. But never heard of someone using Mentor's Monet, though the demo
videos look interesting. ;-) Anyone out there using it?"
- Lars Rzymianowicz, University of Mannheim
"There is little interest in behavioral compilers of any sort. We roll
our eyes at some of this stuff."
- Tom Coonan, Scientific Atlanta
"We are very much a DC and Module Compiler house. DC is still a
workhorse and with a lot of training you can get good results. A
practice we have found is you can never know too much about DC, nor
can you overtrain your people. We have shifted from a few "experts"
to working very hard to get as many people up to speed and well versed
with Synopsys as possible. Synthesis is just too key to the whole
process of chip design. It affects so many things from architecture
on the front end to performance and physical design on the back end
that EVERYBODY needs to understand it and be good at using the tool.
Our designs are very datapath oriented. We have found Module Compiler
to be a very good tool for these types of designs. You can get a huge
bang for the buck in terms of gates/lines of code and significantly
reduce your coding effort for a design. That being said you need to
realize what the tool is good for and what it is NOT good for. Module
Compiler is terrible on control functions, and after many failed
atempts, we have proven conclusivly that you don't use MC on control.
It kicks ass for datapath, which it was design for anyway."
- Phil Hoppes, Intersil
"MODULE COMPILER (MC)
====================
I attended the MC session to get an update. A few interesting notes:
* I'm sure you MC designers already know this, but MC has an fir()
function. I always saw the FIR sample, but I didn't realize MC
had a FIR function.
* From a Scientific Atlanta chip at 0.18u: MC+DC gave them a 37%
speed increase relative to DC only, and MC+PC gave them an
additional 30% speed increase relative to MC+DC due to the
structured layout.
* In the demo of an FFT block with the NEC 0.13u process, MC+PC
predicted area, frequency, and block utilization. After the 1st pass
of a detailed route, the block had identical area and block
utilization, and the frequency changed from 667 MHz to
649 MHz -- that's within 3% of the predicted speed. Also, with
clock gating (via Power Compiler+MC), they achieved 9% area
reduction, a dynamic power reduction from 289 to 280 mW, a static
power reduction from 65 to 1 mW, and no change in timing.
Henry Samueli, co-founder of Broadcom, said they use Module Compiler
heavily, but he also said it still doesn't yield results as good as all
their hand-placed datapaths. He seemed to infer that they still do a
lot of hand-placed datapaths for speed and area optimization."
- [ An Anon Engineer ]
"We use Design Compiler exclusively."
- Paul Schnizlein, Agere Systems
"We've spent so much time getting expert at Synopsys DC that it would
take an act of God to get us to switch. What do you get from moving
to a new synthesizer? 10X performance? 10X larger blocks? I don't
think so!"
- John Szetela of AMD
"We use Synopsys DC. Not thinking of switching. New tools don't have
the library support to even test out."
- [ An Anon Engineer ]
"I'm still a DC junkie. Ambit had some nice features before Cadence,
but lost all it's steam once Cadence bought them. The biggest issue
for me personally these days is being almost forced by Synopsys, after
nearly 10 years of fighting with their tool to switch over to that TCL
beast of a front end. No matter how many times I write a script or
TRY to do something in TCL, it was just EASIER and made sense in the
original DC-shell script.
Foreach in a list was "foreach". No need for "foreach_in_collection".
And collections that are collections of POINTERS to the objects???
ARRGH... [get_attribute <pointer> full_name] ???? Just to find out
what COMPONENT you're actually operating on??? Now don't get me wrong,
I've used DC-shell, TCL, C-shell, Perl, and others to script with, but
the bastardized version of TCL that Synopsys uses... sheesh... If
you're going to say you're going to use TCL then why don't you use TCL
as it is in the 2 books I've got on the subject instead of THINKING you
need to add things to the language and NOT fully explaining what's
going on??? You can see back to an old ESNUG report on how much fun I
had trying to convert some scripts from DC-shell to TCL about 2 years
ago. It ain't much better now... WHY oh why did the Synopsys R&D guys
think that collections of pointers makes more sense than collections of
objects???? Grumble... Friggin' object oriented software guys...
Deeeep breath... Alright, I'm OK now."
- Gzim Derti, Improv Systems
"DC rules!"
- Michael Hede, MindSpeed
"Synopsys DC is still not VHDL-93 compliant and it's hard (imposible?)
to get an overview of all the switches and settings. When you complain
about something, there's often already an undocumented switch for it."
- Menno Spijker, Mitel Semiconductor
"Synopsys hasn't done anything major to their very cumbersome interface
since the 1980's. If I had a good choice I'd drop DC like a rock.
Synopsys is still ahead because of the number of foundries that only
give out libraries in their format, but that's finally changing."
- [ Kenny, from South Park ]
"The biggest lie? Synopsys DC 2000.11:
Seven months after release, it still has many bugs. I have 2 serious
and 8 minor STARs open for 2+ months now and will be waiting another
at least 1-2 months for a fix. SOLVIT and Scout are not being updated
with timely accurate STAR information. Are other people out there
finding that Synopsys QA has very badly slipped in the last year? This
is the sort of negative experience more than pricing that makes people
think of switching."
- [ An Anon Engineer ]
"Some notes to the ACS feature of Design Compiler. We used ACS for the
synthesis of an ASIC with 1.5 million gates, 30,000 lines of Verilog
code, 320 unique modules. ACS is very nice for handling large designs.
Was able to cut the number of scripts from a previous buttom-up compile
approach of about 50 scripts to 12-15 scripts for the ACS flow. Used a
3-step approach: compile, recompile, refine. Discovered a bug in the
initial propagation of top-level constraints down the hierarchy. This
became a STAR. As workaround, we simply dropped the buggy parts from
the acs_compile_design TCL script, and used some default constraints
for subdesigns. Once the first compile was done, the other ACS
commands (recompile, refine) worked fine.
With the newest additions like automated design partitioning, HDL read,
etc., ACS can save you a lot of time. Would recommend it to everyone,
who has to setup a flow for large designs."
- Lars Rzymianowicz, University of Mannheim
"As an ASIC IP company we need to support DC. Our customers haven't
demanded anything else."
- Scott Evans of Sonics, Inc.
"Not much to say about Design Compiler. It pretty much rules our
industry. Just look at the job section and see how many companies
want engineers with expertise in DC as compared to Ambit or any
other synthesis tool."
- Himanshu Bhatnagar of Conexant
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