( DAC 01 Item 23 ) --------------------------------------------- [ 7/31/01 ]
Subject: TetraMax, Fastscan, LogicVision, SynTest, Intellitech, Fluence
MENTOR ON THE ROPES: Three months ago, Gary Smith of DataQuest reported
that the '99 DataQuest numbers gives Synopsys 52.2% vs. Mentor 24.0%
marketshare in the ATPG business. "I see Physical Compiler driving the
dominance of Synopsys in the DFT market, and Mentor's marketshare should
continue to shrink," said Gary at the time. Sad news for Mentor, because
years ago, they used to have a really good rep with the high priests of
chip test. And Synopsys Test Compiler used to be the Tool-That-Everyone-
Bitterly-Complained-About. It's odd how the wheel of fortune can turn.
"Synopsys/Advanced ATPG
Membist IP beta in September 2001. "Coretest" (phase-1 internal scan
based core, 5/02; phase 2 - BIST core, 12/02), enhancements to DFT
Compiler High capacity DFT flow targeting 12/01. Using a modeling
approach to abstract block netlists, enabling top-level scan
stitching of much larger designs more efficiently transparent to the
existing DFT Compiler flow. "CTL" models provide a test abstraction
of block-level netlists. Can use information from CTL models to do
DRC, insertion and stitching. New commands: write_test_model, and
read_test_model."
- [ An Anon Engineer ]
"The gap between TetraMAX and Fastscan is getting smaller, but Fastscan
still has the edge due to its capability in handling sequential
circuits and path delay testing. TetraMAX's built-in debug tool is
better than Mentor's DFTinsight. And if you need to test non-scan
embedded memories or register files, Fastscan's Macrotest has no
competition in the industry."
- Luis Basto, Analog Devices
"I have used both FastScan, 3 years ago and TetraMAX last year. The
TetraMax folks have done a lot to make this tool fast and usable. I
like the control and feedback I get from this tool. From what I have
read, no first hand experience, FastScan has not kept pace. Right now
because of my experience and my client base I would prefer TMAX."
- Tom Tessier, t2design (from SNUG'01 #18)
"Mentor is working on a product for the new P1500 spec for testing cores
(Logicvision has one?), and Mentor and Syntest also has logic and
memory BIST. Syntest is partners with Cadence and I wouldn't be
surprised if Cadence buys them. I also wouldn't be surprised if
Synopsys buys Logicvision to fill their BIST hole (sounds obscene,
doesn't it).
Logicvision sells tools for Built-In-Self-Test (BIST) for both memories
and logic. They will emphasize that technically they are selling IP
(the BIST circuitry they use), which I assume means the software itself
is not that complicated and is easily duplicated. For memories, BIST is
easy because the structures are so regular. The problem with logic BIST
is that you can't just do it from the registers. For example, if
there's a zero detect on an 32 adder output, random patterns would
result in this signal being active only once every 2**32 clocks. Any
logic downstream from it would never be fully tested.
Logicvision has software that identifies where to add extra test points
(like a zero flag) so as to get high coverage with fewer clocks. They
now have software specifically for doing BIST on IP cores. Their tool
provides a list of possible new test points and provides the coverage
improvement for each point. You would then say yes or no to each
recommendation based on timing and size impact. They say their system
may be an add-on to the P1500 spec for testing IP that the IEEE is
working on."
- John Weiland, Intrinsix
"Test insertion: Cadence Ambit's new version of BuildGates supposedly
does a much better job of test insertion. Unfortunately they still
seem to have some problems mostly with gated clock type designs.
Also chains that contain both rising and falling edge flops end up
with lock-up latches between the rising and falling edge flops (instead
of placing all the falling edge flops at the beginning of the chain)
thus obviating the need for lock up latches.
Overall I'm not happy with Ambit's test compiler, but it's a lot better
than what they had previously. (I guess for $12K one can't complain
too much either!)"
- Tom David of Cygnal
"TetraMax is a great tool compared to Test Compiler. We are also using
Formality a lot to do gate-to-gate comparisons during ECO's."
- [ An Anon Engineer ]
"We use TetraMAX. It seems acceptable. But in the future, we may try
Mentor's Fastscan, because we want scan to test timing, and TetraMAX
isn't doing it for us.
We tried an earlier version of BSD Compiler, in January through March
2000, and gave up. We now use Logicvision's JTAG insertion tool. We
like it OK, the advantage is it inserts at RTL level, as opposed to
Synopsys gate level. That allows us to easily simulate, and use formal
equivelence checking. I would not consider BSD Compiler again."
- Paul Schnizlein, Agere Systems
"We are switching to TetraMAX. I did not use Fastscan, only the
original Synopsys Test Compiler. Since my coding style is 'hardware
oriented' and very strict, I had no problems there."
- [ An Anon Engineer ]
"Man, Tmax is cool. Somehow whoever made it convinced Synopsys that
they didn't have to follow Synopsys tool interface conventions. Thank
God for that. Test Compiler is a pain in the butt, I try to hit it
with kid gloves to get something out, and solve all my problems in
TetraMax.
For all you EDA guys out there, look to Tmax for an example of how
online help can be done - connected help to error messages, "What
should I do now" sections on every help page. It has some quirks,
but once you figure out the general way things work, all is well."
- Paul Gerlach of Tektronix (from SNUG'01 #18)
"TI ASIC customers use TetraMAX & FastScan. Both are great tools. TI
ASIC also support LogicVision MemBIST, but I have no direct experience
with QoR."
- [ An Anon TI ASIC Engineer ]
"We've used Fastscan for years. I know that TetraMAX has gotten some
attention from our test team, but I don't anticipate an imminent
change."
- [ An Anon Engineer ]
"At the high end, TI is the only company I know who had done significant
changing of their ATPG vendor. I don't see one tool or the other being
enough better to cause users to switch. The "best" solution is still
IBM ASIC's solution - a vectorless release, they do all the DFT/ATPG
for you. Can't beat that."
- Hank Walker, Texas A&M University
"We have done limited benchmarks between TetraMax and Fastscan.
Fastscan produced slightly better coverage (anywhere from 0.5% to
2.0%) than TetraMax. However, since TetraMax was new to us, maybe
we did not exploit its full capability."
- Himanshu Bhatnagar of Conexant
"We use LogicVision and have found overall this to be a good tool. It
is a pain to integrate into a design flow because it only works on a
gate level netlist so all of those neat RTL tools basically don't work
in your flow because you have to break out after synthesis into this
gate level flow to incorporate LogicVision IP into your design. That
being said, you achive a very high degree of testability in a design
with a modest effort when compared to the degree of difficulty of
using hardware accelerators and such."
- Phil Hoppes, Intersil
"We use LogicVision for memory BIST, and JTAG. We might consider logic
BIST if it wasn't so pricey."
- Paul Schnizlein, Agere Systems
"Intellitech
These people sell a bench top tester. They answered all questions very
vaguely and gave us the impression they were saying "yes" when they
meant "I don't know".
Their product is aimed at executing JTAG scan on chips and boards. We
focused the interrogation on chips. They say that they can handle any
chip that you can put in a socket and that they've worked on chips up
to 1000 balls. They support differential inputs, GTL, HSDL. We don't
think they support SSTL2. The tester runs up to 64 MHz, but can drive
clocks of 60-500 MHz if it's required to initialize the ASIC.
They claim to have Sun (processors) as a client and have been around
for 10 years."
- [ An Anon Engineer ]
"My impression after leaving DAC is that Mentor's FastScan is the
easiest ATPG tool to use. I liked it's ability to read Verilog
(as well as ATPG) format for DFT libraries. I'm considering
creating my own cell libraries, partly to take advantage of the
space savings available from my partners who do full custom layout.
Being able to have the tool read in a Verilog library would be more
convenient for me than having to hand generate a DFT library. Another
plus is that FastScan links in with Cadence's BuildGates, which I'm
considering using.
If vector sets are getting too large (for either tester memory or test
time) FastScan has the ability to identify the most effective vector
sets and reduce the total number of vectors used. This is less
critical for my application, I expect the one-second per chip test
handler time to greatly exceed the time to run vectors for each chip.
LogicVision: These folks had no literature at their booth and the
person manning the booth referred me to people not at the show to have
my questions answered! I prefer vendors to have knowledgeable people
at the show. Walking around the show and talking to other engineers,
I found someone familiar with their product. Based on his experience
it's worth considering, but it sure would be nice talk with a
LogicVision employee who knew their own product.
SynTest: As I discussed buying their tools, a Senior Account Manager
(new) told me that he viewed me as a competitor! (As a consultant, not
as a tool vendor.) Later, reflecting back on this I decided it is
silly to build an alliance and use tools from a vendor who views you
as a competitor. So, the SynTest folks are out.
I wanted to take a look at TetraMax, but ran out of time. Talking with
other consultants over the years, I have picked up the perception that
Synopsys has somewhat less than attractive pricing and licensing terms
for consultants. Because of this, Synopsys was at the bottom of my
priority list."
- Bob Painter of TurnKey Logic
"We purchased TetraMax recently, as part of an upgrade path from Test
Compiler, but have not really exercised it. I heard favorable comments
from other users at DAC, however."
- [ An Anon Engineer ]
"We use Fastscan only because LSI will not formally qualify TetraMAX.
There are several heretics within LSI who use TetraMAX however this is
just one thing where we have decided it's just not worth it. If a
protohold were to happen with scan patterns from TetraMAX we would be
up s--- creek because it's not qualified and we would be on our own as
far as internal support."
- Duncan Halstead, LSI Logic
"Quite happy with FastScan. FlexTest is too slow for our needs.
Evaluated Syntest for a long time, without success, so we dropped it."
- [ An Anon Engineer ]
"Synopsys TetraMAX seems not good enough. It needs to create much more
test patterns than SynTest's to reach high coverage. BTW, SynTest's
tool is more flexible than TetraMAX."
- Jeong-Fa Sheu of Acute Communications
"We use TetraMAX for scan, Logicvision for JTAG/BIST. Works great."
- [ An Anon Engineer ]
"We used LogicVision memBIST tool as it was required by our ASIC vendor.
The LogicVision flow was simple and well documented. Although we are
1st time users, we managed to get thru the finish line in a timely
manner with regard to memBIST and tapBIST/boundary scans."
- [ An Anon Engineer ]
"We're generally sticking with Mentor Fastscan here for now."
- Andrew MacCormack, Tality/Cadence
"I just started using TetraMax and Synopsys DFT Compiler after using
Mentor DFT tools. TetraMax and Fastscan are very similar tools (same
developer if the rumors are correct). The features, syntax and
performance are similar, and both are very good tools.
Comparing Synopsys DFT Compiler and Mentor DFT-Advisor + DFT-Insight,
I prefer the Mentor tools. The quality of both tools is good, but I
couldn't compare performance. It seems that DFT-Advisor is better.
It's very easy to use, and has great debug features. DFT-Insight is
the same tool to debug Fastscan. Synopsys DFT Compiler uses up a
Design Compiler license, which is a big disadvantage for a company
with a limited number of DC licenses."
- [ An Anon Engineer ]
"TetraMAX is the best scan pattern generator for difficult-to-scan
designs. Mentor's Fastscan is fine for not-so-tough designs."
- Carl Wakeland, Creative Advanced Technology Center
"Fastscan seems to get the full scan job done."
- Rick Price of Ensemble
"TetraMAX is standard part of the flow and it "just works" for us."
- Tom Coonan, Scientific Atlanta
"TetraMAX is fast with a very nice user interface and help pages.
Inputs are a Verilog netlist and Verilog library. An optional input
of a STIL file to specify the shift/capture procedures and timing
is a little bit more obscure."
- Kristie Armentrout of Tektronix
"Oddly, I found TetraMAX pretty easy to use and understand. It took a
bit of time to figure out what some error messages actually mean and
a few little quirks of the tool were hard to glean from any docs or
Solvit -- but TetraMAX seems to have all of the bases covered."
- Gzim Derti, Improv Systems
"Genesys makes BIST for logic and memories (including CAMs). Their
memory BIST allows for soft repair of faults (note that the new
Virage memory compilers allow for both soft and hard repair). They
also have a boundary scan insertion tool.
Fluence, the TSSI folks, translate vectors from standard formats
line WGL or STIL to tester-specific formats, and let the test
engineer tweak the inputs and study the outputs from the tester.
They also sell a simulator for fault grading and IDDQ simulation.
They bought Opmaxx, which sells BIST for analog circuits, as well
as tools to measure the quality of your analog tests. Last year
they had BIST to measure jitter in PLLs (which isn't easy on a
tester). This year they've added BIST for DACs, ADCs, amps and
filters.
Simutest does vector translation like Fluence. Don't know how
they differ.
Simucad sells a fault simulator that can distribute simulation
over an arbitrary number of nodes, sort of like Cadence's
Verifault. Note that Verifault running on four nodes is still
much slower than Synopsys Tetramax on a single node, based on
work one of the guys in my group did. Algorithms matter.
Asset and Intellitech do software and hardware to test boards via
boundary scan. You give the tool the netlist for the board and a
description of the boundary scan on each of the parts, and it will
generate tests that check all the chip-to-chip interconnect on the
board. They also sell the testers."
- John Weiland, Intrinsix
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