( DAC 01 Item 19 ) --------------------------------------------- [ 7/31/01 ]
Subject: Real Intent 'Verix'
GREAT RECOVERY: Last year, Real Intent fell flat on its face with those EDA
buyers unfortunate enough to see their demo:
"Intent-o-matic or some name with word Intent in it. This puppy is
suposed to eliminate testbenches completely. It's static, yet it did
show wave forms. Looks like it iterated through 'case' statement loops
and flagged un-fufilled paths. All the examples I saw were small and
could have been caught by a linter. The engineers I was with all walked
off after the guys started arguing that a linter could not catch this
and we all knew that they could. Vaporware or lint-ware.
- Peet James of Qualis (from DAC'00 #18)
"Real Intent 1 star (out of 3 possible)
Verix
Real Intent has a tool called Verix which is touted as an Intent-Driven
Verification tool which uses no testbenches. Instead, it implements a
white-box testing scheme employing various model checks which check the
design. Supposedly, the tools can build upon verification runs of
lower level modules. Seems to be similar to some of the assertion
checkers which are now being marketed, albeit this tool just did not
catch and hold my attention well.
Some of the Design Intent that it "verifies" are rules commonly checked
by a lint tool such as Verilint or some other design purifyer."
- an anon engineer (from DAC'00 #18)
This year things are different. Quite a few people checked them out and had
far better things to say this time around. It's not often that an EDA tool
gets a second chance to recover from a really bad first impression.
"Real Intent and Verplex seem to have similar new generation Model
Checking tools:
* Some "zero effort" automatic checks for bus contention, dead
code, etc.
* Properties are specified inline with the RTL to make context
definition easier
* Properties can also be used in simulation to run assertion
checkers"
- Andrew MacCormack, Tality/Cadence
"Verix by Real Intent
--------------------
1. Properties ('design intent' in their lingo) are described as
assertions using a Verilog-like language. They are embedded in
a design file as Verilog comments.
2. In automatic mode, without any user-defined properties, it verifies
a set of 'implied intents' such as dead code, constant RTL
expressions, constant nets, bus contention, floating buses,
full-case pragma violations, parallel-case pragma violations, etc.
3. It is hierarchical.
4. Verilog monitors can be synthesized from user-defined properties.
They can be used in simulation.
5. Powerful diagnostic tools.
6. Available on Linux/Intel.
7. Subscription fee is about $50K/year.
8. Andy Bechtolsheim is one of the investors."
- Henry So of Mobilygen, Inc.
"Several months ago, we evaluated Real Intent's "Verix Implied Intent"
and "Verix Expressed Intent". What caught our eye:
- Implied Intent required no code modification, but can identify
many real word coding problems, including: Dead code, lint
errors, full_case/parallel_case pragma violations, and constant
assignments/memory elements.
- Implied Intent not only points to pragma violations, but also
dumps VCD files that show how the failing condition is entered.
- Implied Intent required very simple scripts to get up and running
and the error messages are very simple to understand and point
you right to the error in the code in most cases.
- Express Intent allows the designer to build verix checks to verify
the designers expected intent of the code through simple pragmas
and Verilog style coding.
- Express Intent error messages also dumps a VCD file that shows
how the error occurred.
- The Express Intent pragmas, are easily read, and also work as
comments of the designers intent.
We have since become a customer of Real Intent, and have made Verix part
of our signoff criteria for our ASICs."
- Peter Van Doren of Aperto Networks
"Real Intent: Last year this looked like a linter. This year they have
added some useful features. It still has static checkers that can
be added by RTLs in the form of pseudo Verilog (commented out). These
checkers can then statically be evaluated by the tool. Can handle only
Verilog. Can handle hierarchy. It has a cool simulation link that
will make an actual Verilog module and instantiate it so that it will
fire during simulation runs as well. There is a library of checkers to
choose from. Cost about $50k for a seat. Still has the major problem
of getting RTL engineers to use it."
- Peet James, Qualis Design
"I looked at Real Intent/Verix, @HDL/@Verifier, Veritable/Verity-Check,
Verplex BlackTie, and 0-in. X-Tek is also working on low cost
equivalency and model checking, but requires CTL input. Real Intent
seems to be the farthest along. They stressed the ability to check for
the absence of desired properties, as well as the more common check
for presence of undesired properties, and now offer hierarchical
checking. Also, it looks like they currently support VHDL. My
impression, which could be wrong, is that the other tools will do most
or all of what 0-in provides, and then some. Most or all have the
ability to generate a testbench automatically from an error trace.
"User Intent" still needs to be supplied by someone who understands the
design, to get the maximum benefit. Veritable claims higher capacity,
and @HDL claims to analyze more complex sequential behavior, etc. I
have NOT yet evaluated any of these tools -- but would very much like
to do so."
- [ An Anon Engineer ]
"Anyway, what impressed me about Real Intent's demo was that it was
doing a lot of "linty" stuff as fast as other lint tools I have seen
and used, and a few checks that I have not seen others talk about yet.
I was also impressed with its ability to point to the source in a lot
more intelligent manner than just going back to a specific line (i.e.
going to the root cause of the problem, not the place where the
violation was detected.) The model checking part also appeared
promising. They used several acronyms (TLAs) that I don't recall
right now, but the basis for their analysis was quite convincing (and
unlike most other demos, they were willing to talk technical stuff.)"
- Yatin Trivedi, Intrinsix
"When we evaluated it, Real Intent only had "Implied Intent," which is
lint with a bit more brain power. It caught bugs like "a single bit of
this bus is wired to 0x0." Unfortunately, it reported the bug dozens
of times, everywhere the bus was wired or used in an expression. We've
had demos of their newer stuff, "Express Intent," which is more like
the Averent tool. Here the assertions are put directly into the design
files, so the control logic for the assertion is already there, from
the design. Looks like it will save a lot of typing."
- Jeff Deutch, Avici Systems
|
|
