( DAC 00 Item 43 ) --------------------------------------------- [ 7/13/00 ]
Subject: Simplex, CadMos, Sequence 'Copernicus', Cadence 'Assure SI'
SIGNAL INTEGRITY: Blurred in with the RF and the parasitic extraction tools
was the fundamental problem of Signal Integrity issues that crop up once
you're at/below 0.18 um:
"What disappointed me at DAC was the woeful lack of cross-capacitance
solutions. I mean I thought I was out here rubbing two sticks together
trying to make fire, but I got to Los Angeles and found the EDA people
still looking for sticks. The Ultima guys actually showed data in
their booth that their noise tool predicted a lower noise spike than
HSPICE. And this is supposed to impress me how? The Sequence guys at
least have a great extraction story, but even they really don't have
anything yet on xcap. They're still really looking for a silicon
partner to try to tune their models with. For my money, they're the
ones to watch on SI. Avant is trying to rise from the ashes on SI.
Cadence is betting their SI farm on Genesis. Magma & Monterey, you have
to change your whole design flow to get at their SI. Too painful.
Nope, Copernicus isn't anywhere yet, but its the only xcap tool
positioned worth a damn."
- an anon engineer
"Sequence (formerly Frequency Technology) is creating a tool called
Copernicus to use timing and layout information to find and fix signal
integrity problems. It will be ready to find problems in perhaps
October 2000 and fix them perhaps the first quarter of 2001.
Cadence also has a signal integrity tool, Assure SI, which takes timing
information from Pearl (the window where each net might be switching)
and the layout information and produces a delta SDF file for your static
timing analyzer, allowing you to see how badly crosstalk might affect
your timing. Note that Cadence will be discontinuing Pearl at some
point (no schedule yet) so I assume this will have to be integrated into
Ambit eventually.
Moscape does noise analysis, too, but has no information on when
different signals are switching within a clock cycle. It sounds
inferior to tools that do - it would give you spurious results.
CadMos sells a tool that sounds a lot like the Moscape tool. It does
static noise analysis. It doesn't look for a switching signal that slows
down another switching signal, instead it looks for a switching signal
that toggles a static signal (which takes a lot more coupling
capacitance).
Rubicad and Sagantech, who have sold compactors/expanders for years,
have recently tweaked their products to aid in solving signal integrity
problems. They can space nets that have crosstalk problems and widen
runs that have resistivity or electromigration problems."
- an anon engineer
"D2W - Design to Wafer services. They handle the process of interfacing
with the foundry from tapeout, mask creation, wafer mapping, probe card
creation, etc.
CadMOS - a variety of software products to evaluate and correct problem
with on-chip noise and design rule issues."
- an anon engineer
"Simplex and CadMOS looked pretty impressive.
I think Epic is going away - Synopsys lost everyone good in the Epic
group. I think they will buy Si Metrics and push the PrimeTime-based
OLA flow."
- an anon engineer
"Another theme at this DAC could have been "signal integrity". Looked
like CadMos had some interesting stuff here! Of course Simplex is on
top in this stuff for now."
- an anon engineer
"Epic Tools: as usual, good but not nicely integrated with the mother
company Synopsys."
- an anon engineer
"I'm really astonished about the performance and accuracy of the EPIC
'Mill' tools. Even with dynamic circuits and pass transistor logic we
get good results using Powermill and Pathmill, but I heard from some
colleagues at Infineon, that they have some big problems with low
voltage designs.
We will also have closer look to Moscape's CircuitScope and to Sycon's
TeraCell."
- an anon engineer
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