( DAC 00 Item 18 ) --------------------------------------------- [ 7/13/00 ]

Subject: Averant/HDAC, iMODL, Real Intent, Valiosys, Levetate

MARKETING 101:  Finally, EDA start-up HDAC figured out how stupid their name
was in an industry where the biggest conference is called DAC.  HDAC's new
sensible name is "Averant".  Now that they've cleaned that up, how do they
stack against their verification competition?  Averant's start-up rivals
seem to be (in the eyes of the users) iMODL, Real Intent, Valiosys, and
Levetate.


   "Averant: Solidify.  Cisco won a best paper award at Design Con 2000
    about Solidify. They used a memory controler that lets you write some
    simple checkers in this little Verilog-esque language.  These guys were
    sound and level headed.  They said this is for blocks and maybe groups
    of blocks, but not large logic.  Still need to verify, but it does help
    one to quickly verify the block level and will statically do stuff that
    you might not think of.  The Cisco Design Con paper is a good read.
    Solidify looks promising.  Their claim to fame is that those who have
    tried it have found several bugs quickly that Averant does not believe
    verification would have caught.  The learning curve on their little
    static testbenching language is said to be quick and not steep."

        - Peet James of Qualis Design


   "Levetate

        - Formal theorem/assertion prover on RTL code

        - Pretty cool temporal language (more intuitive than Specman's).
          You define events and time points to model your RTL.  You define
          assumptions to model your inputs.  You then state expectations
          as hypothesis that the checker then proves on the RTL.

        - They understand that their tool is block-level only but have
          great hopes for its scalability.

        - Can generate VHDL testbench to illustrate failures.

    I suggested they look into using Specman's temporal expressions but the
    language license cost was an obstacle for them."

        - Janick Bergeron of Qualis Design (VG 1.13)


   "Averant's Solidify is already in use by other groups in [ Company
    Deleted ], but we haven't had time to evaluate it for ourselves.

    iMODL has an interesting concept that we've been using successfully
    for many years now.  I think their tool needs to mature a little more,
    but it is undeniably a great approach to verification.

    Valiosys looks interesting, but I let our Formal guy talk in depth
    with them and haven't followed up to see what the results were.  They
    promise many more state bits than any competitor in the same space, so
    if their claims are true then they have a compelling product.

    Real Intent seems to be a case of marketing hype rather than real
    engineering.  Their Verix tool is basically a glorified lint checker,
    but their booth makes it sound like a full-blown formal verification
    tool.  They were EXTREMELY careful in their spiel to avoid the use of
    ANY formal verification terms, though.  Very clever.  I questioned them
    on that, and they had to back down quite a bit on their claims.  Yeah,
    there's some good stuff in their tool, but not enough to make an entire
    company out of.

    Who won't be around next time?  Real Intent.  Possibly iMODL if they
    don't get any users.  Levetate is a small company that promised blue-sky
    formal verification coverage, but had absolutely nothing to back up
    their claims.  If they show up next year with a useable product, I'll
    eat my hat."

        - an anon engineer


   "Real Intent

        - The tool they demo'ed on the floor looked like a linter to me.  I
          think it embeds checkers a la 0-in, too.  They claim they derive
          "implicit intent" from the RTL code.  Sounds like a euphemism for
          coding guidelines and detection of bad coding practices (aka
          linting).  Important but not that revolutionary.

    In their suite, they had a beta of what they call "explicit intent"
    tool.  I did not have time to go see it but it sounded similar to
    Levetate.  Promising technology..."

        - Janick Bergeron of Qualis Design (VG 1.13)


   "Levetate said they could handle any size design, regardless of the
    number of state bits, in their formal tool suite was the biggest lie I
    heard at DAC.  They promised automatic testbench generation and full
    formal verification coverage, but their demo was a two-latch, five-gate
    design scribbled on a piece of paper.  Absolutely nothing to support
    their claims.  A lie, or a case of eyes-bigger-than-their-stomach?
    Probably the latter, but marketing hype is a gray area."

        - an anon engineer


   "Real Intent                                 1 star (out of 3 possible)
    Verix

    Real Intent has a tool called Verix which is touted as an Intent-Driven
    Verification tool which uses no testbenches.  Instead, it implements a
    white-box testing scheme employing various model checks which check the
    design.  Supposedly, the tools can build upon verification runs of
    lower level modules.  Seems to be similar to some of the assertion
    checkers which are now being marketed, albeit this tool just did not
    catch and hold my attention well.

    Some of the Design Intent that it "verifies" are rules commonly checked
    by a lint tool such as Verilint or some other design purifyer."

        - an anon engineer


   "Intent-o-matic or some name with word Intent in it.  This puppy is
    suposed to eliminate testbenches completely.  It's static, yet it did
    show wave forms.  Looks like it iterated through 'case' statement loops
    and flagged un-fufilled paths.  All the examples I saw were small and
    could have been caught by a linter.  The engineers I was with all walked
    off after the guys started arguing that a linter could not catch this
    and we all knew that they could.  Vaporware or lint-ware.

        - Peet James of Qualis


   "iMODL is one of a small number of companies providing a Foster bus
    model.  We were aware of them before DAC so it wasn't something new.
    Their bus model is synthesizable but there control mechanism is written
    in C.  You can't use this model with acceleration.  Might work well
    with the IKOS co-simulation environment."

        - an anon engineer


   "Levetate sells a tool that is a combination model checker and theorem
    prover.

    Valiosys sells a model checker that they say is superior in its
    explanation of errors.  They say it always gives the shortest
    possible explanation of a error if a theorem isn't true.  They are
    looking for people to OEM the product.  Support would be an issue.
    They're based in France."

        - an anon engineer


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