( ESNUG 556 Item 1 ) -------------------------------------------- [02/01/16]
Subject: SCOOP - Anirudh launches unexpected attack on MENT TestKompress
By 2014, it is common to use stuck-at fault tests and transition fault tests
that are delivered in compressed form inside your chip. That is, pattern
compression (aka MENT TestKompress) was invented as a fix for the need to
get all those vectors past your pin I/O bottleneck.
Early compression/decompression ratios were 5X to 10X. This has since
grown to 100X to 200X -- with some chips achieving up to 1000X.
Wally added the colorful early customer reactions to TestKompress. Because
this technology could clearly save the semi houses 10's to 100's of millions
of dollars, MENT Sales priced it at a "meager $1 million per seat".
Customers balked. Some even started creating their own compression HW in
house. But the technology stuck. Market forces equalized the license fees.
Compression technology is in widespread common use today.
- Luis Basto, DFT consultant
http://www.deepchip.com/items/0538-12.html
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SCOOP!: My spies report that tomorrow Anirudh's group inside CDNS is going
to announce a completely new thrust into the scan test compression market
with a new CDNS tool called "Modus" -- in an EDA niche that's been heavily
dominated by MENT TestKompress, with SNPS DFTmax as second fiddle, and
CDNS DFT Architect in a very very distant 3rd place.
GSEDA 2013 ATPG market share
MENT FastScan & TestKompress : ################ $55 M (46%)
SNPS TetraMAX & DFTmax : ############ $43 M (36%)
CDNS True-Time & DFT Architect : #### $16 M (13%)
"Automatic test pattern generation (ATPG) was a star of the DFT market in
2013. For the 2nd year in a row, annual growth topped 19 percent. Growth
was uneven among the vendors in this segment, with Mentor Graphics and
Cadence seeing more than 30 percent growth a piece, while Synopsys' growth
was just less than 5 percent for the year," said Gary Smith in his 2014
Market Trends report. "One of the brightest spots in the ATPG market is
test compression, which has rapidly become an essential component of device
testing strategies."
Do the math with those growth rates and those numbers today ballpark to:
projected GSEDA 2015 ATPG market share
MENT FastScan & TestKompress : ########################## $93 M (52%)
SNPS TetraMAX & DFTmax : #################### $72 M (39%)
CDNS True-Time & DFT Architect : ##### $18 M (9%)
So got that? At 52% Wally pretty much majority owns scan test with Aart
at 39% playing follow along. Cadence has always been weak in scan test.
Lip-Bu's 9% barely even shows on the radar screen. So for Anirudh to be
making technology advances in test is both unexpected and bizzare.
And how bizzare is bizzare in scan test?
First let's take a quick look at normal everyday scan compression:
At the tester head you serial scan into your chip your compressed vector.
Inside the chip that compressed test vector is decompressed and sent out
to 100's to 1000's of different internal scan strings. The test head gives
the chip one clock cycle. The internal chip registers store the new state.
That new state is compressed in the chip and serially scanned back out.
Scan insertion, ATPG, and scan compression are usually last stage steps in
the design cycle. Typical scan compression is roughly 100X to 200X. Fault
coverage can drop a small percent during the scan compression process. It
also means adding internal test IP can add some mild rerouting issues plus
increase your overall chip die size by 5% to 10%.
Here's where the bizzare comes in.
What my spies tell me is that Anirudh's folks have come up with something
new called "2-D compression" inside their new Modus tool. Here's the
fragments that I know:
- I'm not sure how much Modus is an external SW tool and how much
is new hard IP that's to be added inside your chip.
- There's something new here because CDNS has 10 patents on it.
- Instead of simple scan chain breaking and reordering, where
the scan vectors go from parallel to compressed serial (to
be put into your chip) this new "2-D compression" magically
and mysteriously does some physical mumbo-jumbo during
Innovus PnR to add the 2nd "D" to compression. That is,
normal compression is just a logical reordering. This 2-D
compression does physical reordering of scan chains as they're
added into your design. (Exactly how, I don't know.)
- Now, with this new Modus 2-D compression you're supposedly
getting 300X to 400X compression, instead of the traditional
old school 100X to 200X compression. (How?)
- Also, CDNS is claiming that with Modus scan compression there
will be no added die size to your chip -- instead of the usual
prior 5% to 10% added die size. (How?)
- Also claims Modus scan compression doesn't impact fault coverage
at all. Claims supposed lossless fault coverage. (How?)
So, assuming that my sources are right, it now looks like Anirudh is doing
an out-of-nowhere surprise Big-On-Claims-But-Weak-On-Details attack on
Wally's 52% ownership of scan test.
(And by end-of-business Tuesday we'll know if my spies were right...)
- John Cooley
DeepChip.com Holliston, MA
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